Methods for manufacturing three-dimensional thin-film solar cells

ABSTRACT

Methods for manufacturing three-dimensional thin-film solar cells  100 , using a template. The template comprises a template substrate comprising a plurality of posts and a plurality of trenches between said plurality of posts. The three-dimensional thin-film solar cell substrate is formed by forming a sacrificial layer on the template, subsequently depositing a semiconductor layer, selectively etching the sacrificial layer, and releasing the semiconductor layer from the template. The resulting three-dimensional thin-film solar cell substrate may comprise a plurality of single-aperture unit cells or dual-aperture unit cells. Select portions of the three-dimensional thin-film solar cell substrate are then doped with a first dopant, while other select portions are doped with a second dopant. Next, emitter  525  and base metallization regions  532  are formed.

This application claims the benefit of provisional patent applications60/828,678 filed on Oct. 9, 2006 and 60/886,303 filed on Jan. 24, 2007,which are hereby incorporated by reference.

FIELD

This disclosure relates in general to the field of photovoltaics andsolar cells, and more particularly to methods for manufacturingthree-dimensional (3-D) Thin-Film Solar Cells (TFSCs). Even moreparticularly, the presently disclosed subject matter relates to methodsfor manufacturing 3-D single-aperture and dual-aperture TFSCs.

DESCRIPTION OF THE RELATED ART

Renewable, high-efficiency, and cost-effective sources of energy arebecoming a growing need on a global scale. Increasingly expensive,unreliable, and environmentally-risky fossil fuels and a rising globaldemand for energy, including electricity, have created the need foralternate, secure, clean, widely available, cost-effective,environmentally-friendly, and renewable forms of energy. Solarphotovoltaic (PV) electricity generation using solar cells is uniquelysuited to meet the needs of residential, commercial, industrial, andcentralized utility applications. Key attributes that make solar energyattractive are the abundant, worldwide, point-of-use supply of sunlight,environmental friendliness, scalability (from milliwatts to megawatts),secure point-of-use generation of solar electricity, and excellentdistributed energy economics. The sun provides more energy to the earthin one hour than the annual energy consumption of the entire world. Muchof the earth's surface receives a significant amount of annual sun-hourswhich may be effectively harnessed for clean and secure electricitygeneration. A key driver for this market pull is a rising publicawareness of environmentally-benign technologies. However, due torelatively low solar cell efficiencies (e.g., less than 12% for mostthin-film technologies and roughly 12% to 18% for most crystallinesilicon solar cell technologies), high costs of raw materials (e.g.,silicon for crystalline silicon wafer solar cells) and manufacturingprocesses, limitations on cost-effective and efficient electricalstorage, and a general lack of infrastructure to support solar cellproliferation, to date there has been limited use of this energysolution (currently, electricity generation by solar photovoltaicsaccounts for less than 0.1% of total worldwide electricity generation).

For commercial applications, cost of energy to the end-user (e.g., incents/kWh for electricity) should be sufficiently low and comparable toor even better than that from utility grids using conventionalelectricity generation sources. The solar photovoltaic electricitygeneration, which currently accounts for less than 0.1% of the globalelectricity generation, may be substantially expanded if it achievescost parity with conventional grid electricity. As the costs of solarcells and modules (typically expressed as $/W_(p)) are reduced,grid-tied solar photovoltaic applications are gaining acceptance at anaccelerated pace, making them an attractive option for significantproliferation in electricity generation.

In the price-sensitive solar cell market, two principal technologyoptions exist. On the one hand, crystalline silicon (c-Si) wafers mayserve as the basis for solar cell formation (currently accounting formore than 90% of the solar PV market). On the other hand, thin-film(amorphous and polycrystalline) technologies using silicon and othersemiconductor absorber materials (such as amorphous silicon, CdTe, orCIGS) may offer significant cost advantages compared to crystallinesilicon wafer-based solar cells. These different approaches are atopposite ends of the price-performance scale. Crystalline silicon wafersoffer higher performance, but at higher costs (due to the relativelyhigh cost of starting monocrystalline and multicrystalline siliconwafers). Thin-film technologies may offer lower manufacturing costs, buttypically at lower performance levels (i.e., lower efficiencies). Forboth approaches, the price-per-watt typically increases as cellefficiencies rise (due to higher material and/or manufacturing costs).

Due to a rapid annual growth rate of more than 40% during the past tenyears and the concurrent demands for silicon material by bothsemiconductor microelectronics and solar PV industries, the solar PVindustry has been experiencing a shortage of polysilicon feedstocksupply. The polysilicon feedstock shortage has significantly constrainedthe solar PV industry growth, particularly during the past severalyears. In fact, the solar cell industry currently consumes over half ofthe worldwide production of high-purity polysilicon feedstock. Withinthe last few years, the contract price of polysilicon has increased fromroughly $30/kg to roughly $85/kg, with spot prices exceeding $250/kg.This has led to large increases in the price of monocrystalline andmulticrystalline silicon wafers, which now account for roughly half ofthe total solar module manufacturing cost.

The trend in the mainstream crystalline silicon (c-Si) wafer solar cellindustry has been to scale down wafer thicknesses to below 200 microns(in order to reduce the amount of silicon material in grams used perwatt of solar cell rated peak power). For example, monocrystallinesilicon wafer solar cells are projected to scale down to a thickness ofroughly 120 microns by 2012, from a current wafer thickness of roughly200 microns. Multicrystalline silicon wafer solar cells are projected toscale down to a thickness of roughly 180 microns by 2012, from a currentaverage wafer thickness of roughly 260 microns. This wafer thicknessreduction, however, presents additional challenges related to mechanicalrigidity, manufacturing yield, and solar cell efficiency. Despite itshigh cost, crystalline silicon (c-Si) technology still dominates thesolar cell market, mainly due to higher efficiencies and synergies withthe established microelectronics industry and supply chain. Currently,c-Si accounts for slightly over 90% of the solar cell market (95% whenribbon silicon is included).

Historically, crystalline silicon solar cells have achieved a 20% costreduction for each doubling of cumulative global cell production(measured in megawatts or MW_(p) and gigawatts or GW_(p)). It isprojected that through innovative cost reduction and efficiencyenhancement methods, the cost of electricity derived from grid-connectedrooftop solar photovoltaic modules may become comparable to the cost ofelectricity purchased from the utility grid in five to ten years. A 2005survey of the commercially available monocrystalline silicon andmulticrystalline silicon solar modules reports the solar moduleefficiencies then in the range of 9.1% to 16.1%, with a medianefficiency value of about 12.5%. Commercial crystalline silicon modulesusually show a rapid initial efficiency degradation of 1% to 3%(relative) due to various effects, including photodegradation effects inwafered solar cells (e.g., wafer minority carrier lifetime degradation).Monocrystalline silicon wafer solar cell efficiencies are projected toincrease to roughly 20.5% by 2012, from a current efficiency of roughly16.5% (leading-edge commercially available monocrystalline silicon solarcell and solar module efficiencies are currently about 21.5% and 18%,respectively). Multicrystalline silicon wafer solar cell efficienciesare projected to increase to roughly 18% by 2012, from a currentefficiency level of roughly 15.5%.

State-of-the-art crystalline silicon solar cell manufacturing currentlyuses about 10 grams of high-purity polysilicon feedstock per peak watt(g/W_(p)), resulting in a polysilicon feedstock material cost of about$0.85/W_(p) (assuming a polysilicon price of $85/kg). Over the next fiveyears, the projected trends of solar cell wafer thickness reduction(e.g., to less than 200 micron wafers) and a long-term assumed price ofabout $20/kg for solar-grade polysilicon may reduce the polysiliconfeedstock cost (in g/W_(p)) by about a factor of four to eight to about$0.10/W_(p) to $0.20/W_(p). Thus, any competing solar cell technologiesshould benchmark their manufacturing cost goals against this reduced rawmaterial cost number. For a given cell efficiency, silicon waferthickness reduction presents a prime opportunity for solar cell costreduction by reducing the amount of polysilicon feedstock consumed perwatt of peak solar power.

The cost associated with wire saws, amounting to about $0.25/W_(p) forcurrent silicon solar cells provides another wafer-related costcomponent for silicon wafer solar cells. Innovative and cost-effectivetechnologies that eliminate the kerf losses associated with sawing andslicing should further facilitate silicon solar cell cost reductions. Itis projected that the wafer-based crystalline silicon solar modulemanufacturing cost (which is currently on the order of $2.10 per watt tomore than $2.70 per watt) may be reduced to the range of roughly$1.50/W_(p) to $1.80/W_(p) by the year 2012, in part due to wafer sawingkerf loss reduction to roughly 130 microns by 2012 from the currentvalue of roughly 200 microns. The overall cost reductions forwafer-based crystalline silicon solar cells may come from varioussources including: lower cost polysilicon feedstock, thinner wafers,higher cell-level efficiencies, reduced wafer sawing kerf losses, andincreased economy of scale or manufacturing volume.

State-of-the-art silicon wafer solar cell fabrication facilities (“solarfabs”) typically produce 125 mm×125 mm up to 156 mm×156 mm solar cellstoday. The trend in crystalline silicon wafer solar cells is towardthinner and larger wafers. The monocrystalline and cast (as well asribbon) multicrystalline silicon solar cell wafer thicknesses inleading-edge solar cells used for power generation modules are projectedto be reduced to around 150 and 200 microns, respectively, by around2009-2010. Any cost-effective, high-efficiency, innovative silicon solarcell technology which enables a substantial reduction of the siliconmaterial consumption (e.g., wafer or film thickness) per W_(p) of cellpower compared to the above-mentioned current and projected 2009-2010numbers may offer significant promise as a viable commercial solar celltechnology for solar photovoltaic applications (e.g., residential,commercial, and industrial rooftop as well as large-scale centralizedutilities electrical power generation applications).

Higher solar cell efficiencies have favorable effects on the entiresolar cell value chain and levelized cost of energy (LCOE in $/kWh) dueto reduced material consumption and cost as well as reducedbalance-of-system (BOS) costs (e.g., area-related solar moduleinstallation and inverter costs). The current mainstream commercialcrystalline solar cells provide efficiencies on the order of 14% to 17%.It is expected that the projected crystalline silicon solar cellefficiencies in commercial solar cells may approach around 19% and 17%for monocrystalline and multicrystalline silicon solar cells,respectively, by the year 2009. A key area for new solar cell businessopportunities is development of innovative cell structures andsimplified process flows which may drive efficiencies up while loweringoverall solar cell and module manufacturing costs. For alternative(e.g., thin-film PV) approaches to succeed over the mainstreamwafer-based crystalline silicon solar cell technologies, they shouldprovide higher efficiencies at even lower manufacturing costs comparedto the projected efficiency and cost numbers for the mainstreamwafer-based crystalline silicon solar cells when the new technology isfully commercialized.

Economy-of-scale fab cost reduction associated with high-volume solarfab capacities is a key factor impacting LCOE. The state-of-the-arthigh-volume solar photovoltaic fabs have annual production capacities onthe order of or in excess of 50 MW_(p) to 100 MW_(p) (MW_(p)=1 millionW_(p)). High-volume solar photovoltaic fab capacities are expected toincrease substantially to annual production rates of several hundredMW_(p) or even approaching 1 GW_(p) (GW_(p)=1 billion W_(p)) in thecoming decade. While very-high-volume solar fabs in the range of 100MW_(p) to 1 GW_(p) should facilitate longer term cost reductions(including LCOE) through high-volume manufacturing economies of scale,the relatively high initial fab investment costs, which may easilyexceed $100M, may impose certain limits on solar photovoltaic fabconstruction options. Ideally, the preference may be to developinnovative crystalline silicon solar cell designs and simplifiedmanufacturing processes which facilitate substantial manufacturing costreductions in solar cells and modules even in smaller-scale (and lesscapital intensive) fabs with modest production volumes (e.g., annualproduction volumes in the range of 5 MW_(p) to 50 MW_(p)). This type oftechnology would allow for modest-volume solar photovoltaic fabs withmodest fab setup and operation costs. Reduced fab setup and operationcosts would further facilitate global proliferation of cost-effectivesolar modules, enabling construction of a multitude of very affordablemodest-volume fabs (in contrast to having to set up very expensivehigh-volume fabs in order to achieve sufficient economy of scale formanufacturing cost reduction). Of course, an innovative solar celltechnology that meets the above-mentioned criteria for cost-effective,modest-volume fabs (i.e., meeting the LCOE roadmap requirements even atmodest production volumes in low-cost fabs set up for simplified solarcell processing), may also be applicable to very-high-volume (e.g.,greater than 100 MW_(p)) solar fabs. Such solar photovoltaic fabs cantake further advantage of the economies of scale associated withincreased volume.

Thin-film solar cell (TFSC) technologies (e.g., amorphous silicon, CdTe,and CIGS) require little absorber material (usually much less than 10microns in thickness) to absorb typical standard “Air Mass 1.5” (AM-1.5)solar illumination due to absorption bands that are well matched to thesolar spectrum. The TFSC absorber material may be deposited oninexpensive substrates such as glass or flexible metallic ornon-metallic substrates. TFSCs typically offer low cost, reduced moduleweight, reduced materials consumption, and a capability for usingflexible substrates, but are usually much lower in efficiency (e.g.,usually 5% to 12%). In the case of prior art thin crystalline siliconfilms, there are a number of major problems and challenges with the useof flat silicon films (such as epitaxially growth silicon films withthicknesses below 50 microns) for low-cost, high-performance solarcells. These include: relatively low solar module efficiencies(typically 7% to 12%), field degradation of module efficiencies, scarceand expensive absorber materials (e.g., In and Se for CIGS and Te forCdTe), limited validation of system field reliability, and adverseenvironmental impact of non-silicon technologies such as CIS/CIGS andCdTe.

Prior art FIG. 1 shows process flow 10 for fabricating c-Si TFSCs usingplanar silicon thin-film absorber layers produced by epitaxial silicon.This prior art TFSC fabrication process flow uses several shadow maskprocess steps to form the cell structure. The cell absorber is simply athin planar film of c-Si formed by silicon epitaxial growth processing.The cell uses frontside silicon texturing to improve light trapping anda detached rear aluminum mirror to improve the cell efficiency. Step 12starts with single-crystal p⁺ CZ silicon. Step 14 involveselectrochemical HF etching of silicon to form 2-layer porous siliconcomprising a 1 micron top layer with 20% porosity and a 200 nanometerrear layer with greater than 50% porosity. Step 16 involves a hydrogen(H₂) anneal at 1100° C. for 30 minutes. Step 18 involves epitaxialsilicon growth at 1100° C. using trichlorosilane or SiHCl₃ (depositionrate of 1 micron per minute), forming 2 microns of p⁺⁻Si and 30 micronsof p-Si. Step 20 involves frontside surface texturing by wet KOH etchingto form upright surface pyramids. Step 22 involves the first shadow maskprocess, with LPCVD silicon nitride (SiN_(x)) deposition through ashadow mask to define emitter diffusion windows. Step 24 involves solidsource phosphorus diffusion at 830° C. (to achieve 80 Ω/square for then⁺ doped junction). Step 26 involves the second shadow mask process,with frontside metallization (titanium/Pd/silver grid) by evaporationthrough shadow mask. Step 28 involves emitter surface passivation byhydrogenated PVD or PECVD SiN_(x). Step 30 involves contact frontsidebusbar by a conductive adhesive. Step 32 involves gluing the cellfrontside to MgF₂-coated glass using clear glue. Step 34 involvesseparating the cell from silicon wafer by mechanical stress. Step 36involves the third shadow mask process, with backside aluminummetallization using evaporation through shadow mask. Finally, step 38involves attaching an aluminum reflector at 200 micron spacing from thecell backside.

Prior art FIG. 2 shows another process flow method 40 for fabrication ofsolar cells on silicon wafers with self-aligned selective emitter andmetallization. This prior art process uses laser processing to patternthe top cell dielectric layer while melting the underlying silicon toform the heavily-doped n⁺⁺ emitter contact diffusion regions (afterformation of the lightly diffused selective emitter regions by rapidthermal annealing). Step 42 starts with single-crystal p-type silicon.Step 44 involves saw damage removal etch and anisotropic texturing etchin dilute NaOH at 90° C. Step 46 involves spin-on application and dryingof phosphorus diffusion source. Step 48 involves rapid thermal annealingto form lightly diffused emitter (80 to 200 Ω/square). Step 50 involvesapplication of backside metal contact by vacuum evaporation or screenprinting of aluminum or silver/aluminum alloy, followed by drying. Step52 involves backside metal sintering/firing (e.g., at 820° C. inoxygen/nitrogen) for a screen-printed contact (fires the metal pastewhile oxidizing the dielectric to raise its resistance to the metalplating solution). Step 54 involves laser processing to pattern the topdielectric layer while melting the underlying silicon to form the n⁺⁺contact diffusion region. Step 56 involves dilute HF etch to preparemetal plating surface. Step 58 involves electroless nickel plating at90° C. for five minutes. Step 60 involves nickel sintering at 350° C. to450° C. (in nitrogen, argon, or forming gas). Step 62 involves anadditional 2 minutes of nickel plating followed by long electrolesscopper plating to form thick high-conductivity copper film. Step 64involves flash immersion silver (silver) deposition on copper surface.Finally, step 66 involves edged junction isolation (e.g., using lasergrooving, edge cleavage, or plasma etching).

With regard to the prior art crystalline silicon (c-Si) thin-film solarcell (TFSC) technology, there are difficulties associated withsufficient surface texturing of the thin silicon film to reduce surfacereflectance losses, while reducing the crystalline silicon filmthickness. This places a limit on the minimum flat (co-planar)monocrystalline silicon thickness due to production yield and cellperformance (efficiency) considerations. In the case of a flat orco-planar film, it is essential to use surface texturing since thereflectance of an untextured crystalline silicon film is quite excessive(can be greater than 30%) and results in substantial optical reflectionlosses and degradation of the external quantum efficiency. Thus,reduction of reflectance-induced photon losses in co-planar epitaxialsilicon films requires effective surface texturing which itself places alimit on the minimum epitaxial silicon layer thickness. Depending on thefilm surface texturing requirements and processes, the minimumcrystalline silicon layer thickness may be on the order of at least 10microns (so that the texturing process does not break through anyportions of the crystalline silicon layer).

In addition, substantially reduced mean optical path lengths in thinplanar crystalline silicon films result in reduced photon absorption,particularly for photons with energies near the infrared bandgap ofsilicon (800 to 1100 nanometers), resulting in reduced solar cellquantum efficiency (reduced short-circuit current or J_(sc)). Thisresults in serious degradation of the solar cell efficiency due toreduced cell quantum efficiency and reduced J_(sc). For instance, in aco-planar (flat) crystalline silicon absorber layer with thickness of 20microns, a solar light beam impacting the cell at a near-normal anglewould have an effective path length equal to the film thickness, far tooshort for the solar radiation photons with energies near the infraredbandgap of silicon (i.e., with wavelengths of roughly 800 to 1100nanometers) to be absorbed effectively in the silicon thin film. Infact, a reduction of the active cell silicon thickness to below roughly50 microns results in appreciable reduction of J_(sc) and the resultingsolar cell efficiency, with this degradation effect rapidly acceleratingwhen the silicon film thickness is reduced below roughly 20 microns.Thus, a co-planar thin crystalline silicon film may also requireeffective light trapping using both top surface texturing and rearsurface back reflection of the light exiting the back surface of thecrystalline silicon film in order to create effective optical pathlengths equal to a large multiple of the crystalline silicon filmthickness.

The prior art technologies using this approach mostly use either backreflection through internal reflection of the light at the crystallinesilicon film/silicon substrate, or reflection from a blanket backsidecontact (such as a back surface field aluminum contact/mirror). The backreflectance provided by these techniques may not be great (e.g., roughly70% effective near-IR rear reflectance), constraining the performancegain that would have otherwise been achieved by an optimal backreflector. The problem with this approach is that the primary incidentbeam always passes the crystalline silicon film only once. Anysubsequent second passes of the primary incident beam photons aredependent on the back surface reflection.

There is also the problem of lack of rigidity and mechanical support ofthe thin film during cell and module processing steps. This problemrelates to the mechanical strength of a large-area (e.g., 200 mm×200 mm)thin silicon film. It is well known that reducing the large-areacrystalline silicon wafer thickness to below 100 microns results in asubstantial loss of TFSC substrate mechanical strength/rigidity, andsuch thin wafers tend to be flexible and very difficult to handlewithout breakage during cell fabrication process flow.

Large-area, co-planar (flat) crystalline silicon films thinner than, forinstance, 50 microns must be properly mounted and supported on acost-effective support or handle substrate in order to achieveacceptable yield for solar cell and module manufacturing. One approachis to grow and retain the thin epitaxial film on a relatively low-cost(e.g., metallurgical-grade) silicon substrate (over which the epitaxiallayer is grown); however, this approach suffers from some inherentproblems constraining the ultimate solar cell efficiency. Anotherapproach is to release or lift off the epitaxial silicon film from its(reusable) parent silicon substrate and subsequently place it on acheaper non-silicon support or handle substrate to provide mechanicalstrength through the solar cell process flow. This approach may sufferfrom any thermal coefficient of expansion (TCE) mismatch between thesupport/handle substrate and silicon film during any high-temperatureoxidation and anneal processes, as well as potential contamination ofthe thin epitaxial silicon film from the non-silicon support substrate(both creating possible manufacturing yield and performance/efficiencydegradation problems).

The cost of the monocrystalline silicon film growth process usingsilicon epitaxy, particularly for thicker epitaxial films withthicknesses in excess of 30 microns is an additional issue which shouldbe addressed. Using a relatively small epitaxial film thickness (in oneembodiment, much below 30 microns) may lower the cost of epitaxy to anattractive range. However, this would present various challenges forfabrication of planar silicon thin-film solar cells. As stated, thinnerco-planar (flat) epitaxial films (e.g., in the range of much less than30 microns) produce a number of problems and challenges, including alack of film mechanical strength, constraints limiting effective surfacetexturing of thin silicon films for low surface reflectance and reducedoptical reflectance losses, relatively short optical path lengths, andreduced cell quantum efficiencies. Effective light trapping is essentialfor enhanced thin-film c-Si solar cell efficiencies. The requirement foreffective light trapping is based on a combination of front surfacetexturing and back surface mirror, while achieving sufficiently lowsurface recombination velocities (for high cell efficiencies). This isvery difficult to achieve in the co-planar (flat) c-Si thin film solarcells.

High-performance c-Si thin-film solar cells require some patterningsteps or patterned processing steps (e.g., for formation of selectiveemitter, frontside emitter or backside emitter wrap-throughmetallization contacts, backside base metallization contacts, etc.).These patterning steps are usually achieved using photolithography,screen printing, and/or shadow-mask deposition (e.g., shadow-masksputtering or evaporation) processes. The use of photolithography and/orscreen printing and/or shadow-mask deposition patterning steps usuallyincreases the manufacturing process flow complexity and cost, and mayalso detrimentally impact the fabrication yield as well as the ultimateachievable solar cell efficiency.

Therefore a need has arisen for a thin-film solar cell (TFSC) whichcorrects the problems identified above.

Yet a further need exists to address shortcomings of existing mainstreamc-Si solar cell technology. This includes reducing the amount ofpolysilicon feedstock consumed per peak watt of solar power, andeliminating the kerf losses associated with sawing and slicing; thus,substantially reducing the overall solar cell manufacturing cost.

A further need exists for innovative solar cell structures andsimplified process flows, increasing cell and module efficiencies whilesignificantly lowering the overall solar cell and module manufacturingcosts. A still further need exists for innovative c-Si solar celldesigns and simplified self-aligned manufacturing processes whichfacilitate substantial solar cell and module cost reduction even in fabswith modest production volumes, enabling low to mid-volume solar cellfabs with modest fab setup and operation costs (thus, achievingeconomies of scale for manufacturing cost reduction at substantiallylower fab volumes than the prior art fabs).

A still further need exists to address shortcomings of existing TFSCtechnology. This includes addressing difficulties associated withsufficient surface texturing of the thin planar silicon films to reducesurface reflectance losses, which currently places a limit on theminimum flat (co-planar) crystalline silicon thickness due to productionyield and cell performance considerations. A still further need existsfor effective light trapping based on a combination of front surfacetexturing and back surface mirror, while achieving low surfacerecombination velocities (for high cell efficiencies).

A still further need exists to address additional shortcomings ofexisting TFSC technologies. This includes the problem of lack ofrigidity and mechanical support of the thin film substrate during celland module processing steps, thus, necessitating the use of support orhandle substrates (made of silicon or another material) for the TFSCsubstrates. This further includes the cost of the epitaxial silicon filmgrowth process, particularly for thicker epitaxial films required forplanar crystalline silicon TFSCs. This further includes the requirementof multiple photolithography and/or screen printing and/or shadow-maskprocessing/patterning steps which usually increase the manufacturingprocess flow complexity and cost, and may also detrimentally impact thefabrication yield as well as the ultimate achievable solar cellefficiency.

SUMMARY

In accordance with the present disclosure, methods for manufacturingthree-dimensional thin-film solar cells (3-D TFSCs) are provided. The3-D TFSCs of the disclosed subject matter substantially eliminate orreduce disadvantages and problems associated with previously developedsemiconductor wafer-based solar cells as well as TFSCs, both in terms ofconversion efficiency as well as cell and module manufacturing costs.

According to one aspect of the disclosed subject matter, there is aprovided a method for manufacturing a 3-D TFSC. The method comprisesforming a 3-D TFSC substrate using a template. The template comprises atemplate substrate comprising a plurality of posts and a plurality oftrenches between said plurality of posts. The 3-D TFSC substrate isformed by forming a sacrificial layer on the template, subsequentlydepositing a semiconductor layer, selectively etching the sacrificiallayer, and releasing the semiconductor layer from the template. Selectportions of the resulting 3-D TFSC substrate are then doped with a firstdopant, and other select portions are then doped with a second dopant.Next, emitter and base metallization regions are formed.

More specifically, the top of the resulting 3-D TFSC substrate isselectively (with spatial selectivity) coated with a first dopant. Ifnecessary, this first dopant is then dried and/or cured. The bottom ofthe resulting 3-D TFSC substrate is selectively (with spatialselectivity) coated with a second dopant. If necessary, this seconddopant is then dried and/or cured. Next, emitter and base contactmetallization regions are formed. Optionally, the resulting 3-D TFSC maybe mounted on a rear mirror for improved light trapping and conversionefficiency.

These and other advantages of the disclosed subject matter, as well asadditional novel features, will be apparent from the descriptionprovided herein. The intent of this summary is not to be a comprehensivedescription of the claimed subject matter, but rather to provide a shortoverview of some of the subject matter's functionality. Other systems,methods, features and advantages here provided will become apparent toone with skill in the art upon examination of the following FIGURES anddetailed description. It is intended that all such additional systems,methods, features and advantages be included within this description, bewithin the scope of the accompanying claims.

BRIEF DESCRIPTIONS OF THE DRAWINGS

The features, nature, and advantages of the disclosed subject matter maybecome more apparent from the detailed description set forth below whentaken in conjunction with the drawings in which like referencecharacters identify correspondingly throughout and wherein:

FIG. 1 (PRIOR ART) shows a prior art process flow for fabricatingcrystalline silicon (c-Si) thin-film solar cells (TFSCs) using planarsilicon thin-film absorber layers produced by silicon epitaxy;

FIG. 2 (PRIOR ART) shows a prior art process flow for fabrication ofsolar cells on silicon wafers including self-aligned selective emitterand metallization;

FIG. 3 (PRIOR ART) summarizes the key process steps eliminated by thecurrent disclosure, compared to the prior art;

FIG. 4 summarizes the high-level process flow and the competitiveadvantages of the current disclosure, compared to the prior art;

FIG. 5 provides another summary of the key features and benefits of thecurrent disclosure;

FIG. 6 shows a top view of an embodiment of a hexagonal-prism TFSCincluding a square-shaped hexagonal-prism 3-D TFSC substrate with aplanar peripheral silicon frame;

FIGS. 7A and 7B show scanning electron microscopic views of twoembodiments of a hexagonal-prism 3-D TFSC, without and with a rear baselayer, respectively (7A and 7B show the dual-aperture andsingle-aperture TFSC substrates, respectively);

FIG. 8 provides an overview of the 3-D TFSC substrate and solar cellfabrication process flow;

FIG. 9 shows a view of an embodiment of a template including hexagonalprism posts;

FIGS. 10A and 10B show magnified scanning views (with two differentmagnifications) of one embodiment of a template including hexagonalprism posts;

FIG. 11 shows a view of an embodiment of a template including staggered(shifted) square prism posts;

FIG. 12 shows a 3-D cross-sectional view of an embodiment of asingle-aperture hexagonal-prism 3-D TFSC substrate (i.e., TFSC substratewith an integral base layer), including the substrate rearmonolithically (integrally) connected to a substantially flat planarthin semiconductor film;

FIG. 13 shows the Y-Y and Z-Z cross-sectional axes on an embodiment of ahexagonal-prism (honeycomb) 3-D TFSC substrate;

FIG. 14A shows a Y-Y cross-sectional view of an embodiment of a singleaperture hexagonal prism 3-D TFSC substrate, while FIG. 14B shows a Z-Zcross-sectional view;

FIGS. 15 through 20 show alternative process flow embodiments forfabricating hexagonal-prism 3-D TFSCs using single-aperture TFSCsubstrates including rear base layers;

FIG. 21 shows a schematic view of a double-sided coater setup forself-aligned application (coating) of dopant liquid or paste layers on3-D TFSC substrate hexagonal-prism top ridges and hexagonal-prism rearsurface or ridges by roller coating and in-line curing of the appliedliquid/paste layers (shown in conjunction with an integrated belt-drivenprocess equipment);

FIG. 22 shows a view of an alternative spray coater and curing setup toperform the same processes as the roller coater and curing setup of FIG.21;

FIG. 23 shows a view of another alternative setup design usingliquid-dip coating or liquid-transfer coating to perform the sameprocesses as the roller coater and curing setup of FIG. 21 and the spraycoater and curing setup of FIG. 22;

FIG. 24 shows multiple adjacent hexagonal-prism unit cells, aftercompletion of the TFSC fabrication process and after mounting the cellrear base side onto a rear mirror;

FIGS. 25A through 27A show Y-Y cross-sectional views of a unit cellwithin an embodiment of a single-aperture hexagonal-prism 3-D TFSCsubstrate including a rear base layer;

FIGS. 27B through 31 show Y-Y cross-sectional views of an embodiment ofa single-aperture hexagonal-prism 3-D TFSC substrate including a rearbase layer, and including either a detached or an integrated rearmirror;

FIG. 32 outlines an embodiment of a process flow for fabrication of atemplate using photolithography patterning;

FIG. 33 shows a top view of an embodiment of a lithography mask designto produce a hexagonal array (honeycomb) pattern;

FIGS. 34 through 37 outline various embodiments of process flows forfabrication of a template using either direct laser micromachining orphotolithography patterning;

FIG. 38 shows the Y-Y and Z-Z cross-sectional axes on an embodiment of ahexagonal-prism (honeycomb) 3-D TFSC substrate;

FIGS. 39 and 40 show Y-Y cross-sectional views of an embodiment of atemplate including through-wafer and within-wafer trenches,respectively;

FIGS. 41 through 47 show Y-Y cross-sectional views of a siliconsubstrate during the fabrication process flow for making an embodimentof a template based on the process flows of FIG. 36 or FIG. 37;

FIGS. 48 through 52 show Y-Y cross-sectional views of alternativeembodiments of templates;

FIGS. 53 and 54 show embodiments of mask designs for patterning asemiconductor (silicon) wafer rear to produce backside openings on atemplate;

FIG. 55 shows an alternative frontside lithography mask with an array ofhexagonal array openings for formation of template trenches and an arrayof holes for formation of an array of release channels from the templatebackside to the template frontside;

FIG. 56 shows the frontside patterning mask in FIG. 55 with a backsidesquare array pattern (to be used for backside patterning with relativealignment as shown to the frontside pattern) superimposed for reference;

FIG. 57 shows the backside lithography mask pattern (square array) inFIG. 56 with the frontside mask hexagonal array pattern from FIG. 55superimposed for reference;

FIGS. 58 through 66 show Y-Y cross-sectional views of a semiconductor(silicon) substrate during the fabrication process flow for making anembodiment of a template based on the process flows of FIG. 36 or FIG.37;

FIGS. 67 through 75 show Y-Y cross-sectional views of a siliconsubstrate during the fabrication process flow for making an embodimentof a template based on the process flows of FIG. 36 or FIG. 37;

FIG. 76 and FIGS. 79 through 86 show Y-Y cross-sectional views of asemiconductor (e.g., silicon) substrate during the fabrication processflow for making an embodiment of a template based on the process flowsof FIG. 36 or FIG. 37;

FIGS. 77 and 78 show backside lithography mask designs; FIG. 78 showsthe relative alignment of the backside square array pattern with respectto the frontside hexagonal array pattern whereas FIG. 77 shows thebackside square array pattern used for formation of chemical releasechannels on the template.

FIGS. 87 and 88 show cross-sectional views of stacked templatestructures for concurrently fabricating and releasing twohexagonal-prism 3-D TFSC substrates per process pass (FIGS. 87 and 88show the stacked templates with in-wafer trenches and through-wafertrenches, respectively);

FIGS. 89 and 90 show alternative embodiments of a process flows forfabrication of self-supporting hexagonal prism 3-D TFSC substratesincluding rear base layers (single-aperture TFSC substrates withsingle-aperture unit cells);

FIGS. 91 through 95 illustrate Y-Y cross-sectional views of a templatewith in-wafer trenches and no dielectrics on the template frontside, asit goes through the key process steps to fabricate a hexagonal prism 3-DTFSC substrate (single-aperture TFSC substrate) with a rear base layer;FIGS. 94 and 95 show the released 3-D TFSC substrate with a base layerand the reusable template after the 3-D TFSC substrate release,respectively.

FIGS. 96 through 98 illustrate Y-Y cross-sectional views of the templatein FIG. 66 with the rear-to-front release channels, as it goes throughthe key process steps to fabricate a hexagonal-prism 3-D TFSC substrate(single-aperture TFSC substrate) with a rear base layer (template ismade on <100> silicon substrate);

FIGS. 99 through 101 illustrate Y-Y cross-sectional views of thetemplate in FIG. 75 with the rear-to-front release channels, as it goesthrough the key process steps to fabricate a hexagonal-prism 3-D TFSCsubstrate (single-aperture TFSC substrate) with a rear base layer(template is made on <110> silicon substrate);

FIGS. 102 through 104 illustrate Y-Y cross-sectional views of thetemplate in FIG. 85 with backside release channels aligned to the bottomof hexagonal-prism trenches, as it goes through the key process steps tofabricate a hexagonal-prism 3-D TFSC substrate with a rear base layer(single-aperture TFSC substrate);

FIGS. 105A through 111C show examples of several embodiments of 3-Dpolygon-prism TFSC substrates including various prism unit cellgeometrical designs and arrangements;

FIGS. 112 through 117 show alternative process flow embodiments forfabricating hexagonal-prism 3-D TFSCs using dual-aperture TFSCsubstrates without rear base layers;

FIG. 118A shows a schematic Y-Y cross-sectional view of an embodiment ofa self-supporting (free-standing) hexagonal-prism dual-aperture 3-D TFSCsubstrate (without a base layer) including a thin peripheralsemiconductor (silicon) frame, before 3-D TFSC fabrication;

FIG. 118B shows a schematic Y-Y cross-sectional view of the 3-D TFSCsubstrate of FIG. 118A after TFSC fabrication;

FIG. 119A shows a schematic Y-Y cross-sectional view of an embodiment ofa self-supporting (free-standing) hexagonal-prism dual-aperture 3-D TFSCsubstrate including a thick peripheral semiconductor (silicon) frame,before TFSC fabrication;

FIG. 119B shows a schematic Y-Y cross-sectional view of the TFSCsubstrate of FIG. 119A after cell fabrication;

FIG. 120 shows a top view of an embodiment of a regular (equilateral)hexagonal-prism 3-D TFSC substrate;

FIG. 121 shows a 3-D view of an embodiment of a hexagonal-prism 3-Dthin-film semiconductor substrate after release and removal from atemplate;

FIG. 122A shows a schematic Y-Y cross-sectional view of an embodiment ofa dual-aperture hexagonal-prism 3-D TFSC substrate, while FIG. 122Bshows a Z-Z cross-sectional view of the same substrate;

FIGS. 123A through 124B show schematic Y-Y cross-sectional views of asingle unit cell from a dual-aperture 3-D TFSC substrate within anembodiment of a hexagonal-prism 3-D TFSC fabricated using a 3-D TFSCsubstrate without a rear base layer;

FIGS. 125A and 125B show Y-Y cross-sectional views of a single unit cellfrom a dual-aperture 3-D TFSC substrate after mounting the cell onto arear mirror;

FIGS. 126A through 127 show Y-Y cross-sectional views of multiple unitcells from a dual-aperture 3-D TFSC substrate, after mounting onto arear mirror (with and without a spacing between the mirror and the rearcell);

FIGS. 128A through 132 show schematic Y-Y cross-sectional views of anembodiment of a hexagonal-prism 3-D TFSC formed on a dual-aperture 3-DTFSC substrate without a rear base layer, with substantially verticalhexagonal-prism sidewalls;

FIGS. 133A and 133B show 3-D views of a single unit cell in adual-aperture hexagonal-prism 3-D TFSC substrate, before and afterself-aligned base and emitter contact metallization, respectively;

FIG. 134 shows multiple adjacent hexagonal-prism unit cells, aftercompletion of the TFSC fabrication process and after mounting the cellrear base side onto a rear mirror;

FIG. 135 shows an embodiment of a process flow for fabrication ofself-supporting hexagonal prism 3-D TFSC substrates using layer releaseprocessing;

FIGS. 136 through 141 show alternative embodiments of process flows forfabrication of self-supporting hexagonal-prism (as well as other prismarray patterns) 3-D TFSC substrates without rear base layers (to formdual-aperture TFSC substrates; i.e., TFSC substrates with top and bottomunit cell openings);

FIGS. 142 through 146 show Y-Y cross-sectional views of the evolution ofone prism unit cell of a template with through-wafer trenches, as itgoes through several key process steps for fabricating a hexagonal-prism3-D TFSC substrate (dual-aperture TFSC substrate) without a rear baselayer;

FIGS. 147 through 150 illustrate Y-Y cross-sectional views of anembodiment of a template with in-wafer trenches and no dielectric layerson the template frontside or template backside, as it goes throughseveral key process steps for fabricating a hexagonal-prism 3-D TFSCsubstrate (dual-aperture TFSC substrate) without a rear base layer;

FIGS. 151 through 154 illustrate Y-Y cross-sectional views of anembodiment of a template with through-wafer trenches and no dielectricson the template frontside, as it goes through several key process stepsfor fabricating a hexagonal-prism 3-D TFSC substrate (dual-aperture TFSCsubstrate) without a rear base layer;

FIG. 155 shows a schematic view of a single unit cell from an embodimentof a hexagonal-prism 3-D TFSC substrate for reference including certainTFSC substrate calculations;

FIG. 156 shows a graph of the computed 3-D TFSC substratehexagonal-prism area ratio (ratio of 3-D cell surface area to the flatcell base area) versus hexagonal-prism aspect ratio (unit cell height toaperture diameter ratio);

FIG. 157 shows a graph of the ratio of the hexagonal-prism TFSCsubstrate mass to a reference flat semiconductor wafer mass for bothtypes of 3-D honeycomb-prism TFSC substrates (single and dual aperturesubstrates), versus various ratio of the honeycomb-prism sidewallsilicon thickness to the reference flat silicon wafer thickness;

FIG. 158 shows a schematic diagram of ray tracing for solar raysincident on a dual-aperture hexagonal-prism unit cell employingreflective emitter metallization contact;

FIGS. 159 through 162 show various numbers of solar light rays incidentat various angles of incidence, demonstrating efficient light trappingcharacteristics of the current disclosure;

FIG. 163 shows simulated light trapping in a unit cell and short circuitcurrent density versus angle of incidence for various emitter contactmetallization embodiments of the solar cell designs of the currentdisclosure;

FIG. 164 shows Standard Test Condition (STC) cell efficiency andshort-circuit current density for the solar cell of the currentdisclosure versus unit cell prism height;

FIG. 165 shows maximum photocurrent density versus incident angle, alsoindicating the effect of emitter contact metallization (assuming 100%optical reflectance for emitter contact metal);

FIG. 166 shows a graph of the representative selective emitterphosphorus and 3-D TFSC substrate boron doping profiles inhexagonal-prism 3-D TFSCs of this disclosure, shown with graded borondoping profile to create a built-in electric field;

FIG. 167 serves as a reference FIGURE for calculation of thehexagonal-prism TFSC internal ohmic losses due to the base current alongthe hexagonal-prism vertical sidewalls;

FIG. 168 shows maximum base resistivity and approximate p-type basedoping concentration values for various 3-D honeycomb-prism sidewallfilm thicknesses in order to limit the base current ohmic losses to lessthan 0.1%;

FIG. 169 shows various views of silicon frames and silicon frame sliversfor the hexagonal-prism TFSCs of the current invention;

FIG. 170 shows a view of series connections of TFSCs in a solar moduleassembly;

FIG. 171 shows a view of the frontside metallization pattern of aprinted-circuit board (PCB) used for solar module assembly using theTFSCs of the current disclosure;

FIGS. 172 and 173 show views of the backside metallization pattern of aPCB used for solar module assembly using the TFSCs of the currentdisclosure;

FIG. 174A shows an enlarged top view of the frontside of a solar modulePCB, showing one of the PCB patterned metallization sites for placementof one of the solar cells of the current disclosure;

FIG. 174B shows an enlarged top view of the backside of a solar modulePCB, showing the series connections of the adjacent cells on the PCB;

FIG. 175 shows a cross-sectional view of an embodiment of a solar modulestructure comprising the TFSCs of the current disclosure and a temperedglass cover;

FIG. 176 shows an embodiment of a process flow for fabrication of solarmodules using a tempered glass cover;

FIG. 177 shows a cross-sectional view of an embodiment of a solar modulestructure comprising the TFSCs of the current disclosure and a coatedlayer cover;

FIG. 178 shows an embodiment of a process flow for fabrication of solarmodules without a tempered glass cover;

FIGS. 179 and 180 show cross-sectional views of a solar glass assemblyfor building façade applications;

FIG. 181 shows a view of an electrically conductive layer formed on aglass plate to interconnect cells in series for solar glassapplications;

FIG. 182 shows an embodiment of a process flow for fabrication of solarmodules for solar glass applications;

FIG. 183 serves as a reference FIGURE for calculation of TFSCinterconnect ohmic losses; and

FIGS. 184 through 189 show graphs of interconnect (emitter contactmetallization) ohmic losses at maximum cell power versus the ratio ofemitter contact metal coverage height for various emitter metal sheetresistance values.

DETAILED DESCRIPTION OF THE SPECIFIC EMBODIMENTS

Preferred embodiments of the present disclosure are illustrated in thedrawings, like numbers being used to refer to like and correspondingparts of the various drawings. The innovative solar cell designs andtechnologies of the current disclosure are based on the use of athree-dimensional (3-D), self-supporting, doped (in one embodiment,in-situ-doped) semiconductor thin film, deposited on and released from areusable crystalline (embodiments include monocrystalline ormulticrystalline silicon) semiconductor template.

A preferred semiconductor material for the 3-D TFSC substrate iscrystalline silicon (c-Si), although other semiconductor materials mayalso be used. One embodiment uses monocrystalline silicon as the thinfilm semiconductor material. Other embodiments use multicrystallinesilicon, polycrystalline silicon, microcrystalline silicon, amorphoussilicon, porous silicon, and/or a combination thereof. The designs hereare also applicable to other semiconductor materials such as germanium,silicon germanium, silicon carbide, a crystalline compoundsemiconductor, or a combination thereof. Additional applications includecopper indium gallium selenide (CIGS) and cadmium telluridesemiconductor thin films.

The 3-D TFSC designs and production technologies as well as associatedmodule structures and assembly approaches of this disclosure effectivelyovercome the above-mentioned problems and challenges and enablecost-reduced fabrication of very-high-efficiency solar cells and modulesusing self-aligned cell process flows without the use of anyphotolithography patterning or screen printing or shadow-mask depositionprocess steps during cell fabrication (i.e., during 3-D TFSC substrateand cell fabrication after fabrication of the reusable 3-D template).The 3-D TFSC technologies of this disclosure are based on the formationof a 3-D prism-array TFSC substrate structure on a low-cost reusabletemplate and its subsequent release and lift-off from the template toform a free-standing, self-supporting 3-D thin-film semiconductorsubstrate structure.

The current disclosure combines the benefits of TFSC fabrication on aproven high-efficiency crystalline silicon (c-Si) platform. The 3-D c-SiTFSC designs and technologies of this disclosure enable significantadvancements in the areas of c-Si solar cell and module efficiencyenhancement as well as manufacturing cost reduction. Based on innovativethin-film process steps, dependence on an expensive and constrainedsilicon wafer supply-chain is eliminated. Some of the unique advantagesof the cells designs and technologies of this disclosure which enableachieving ultra-high-efficiency at reduced manufacturing cost aresubstantial decoupling from the traditional solar PV silicon supplychain, performance enhancement, cost reduction, and reliabilityimprovement.

The disclosed subject matter improves solar cell efficiency by using a3-D c-Si film as an absorber layer in conjunction with highly efficientlight trapping. Use of the crystalline silicon absorber layer leveragesknown solar cell manufacturing techniques and supply chain, whilereducing absorber layer thickness (e.g., reduced by a factor of ten ormore compared to silicon wafers used for wafer-based solar cells). Thedisclosed method and system eliminates or substantially reducesphoto-degradation and enhances open-circuit voltage (V_(oc)) of cells.In addition, the disclosed method and system provides efficientfrontside and rear side light-trapping in conjunction with a highlyreflective rear mirror for maximum absorption of incident solar flux.Also, the disclosed method and system provides a selective emitter toenhance blue response and external quantum efficiency, with minimalshadowing of the cell and reduced ohmic losses due to a unique foldedemitter metallization contact design and improved module assembly.

Manufacturing cost is reduced by decreasing silicon usage (by asignificant factor, e.g., 3× to over 10×), with thinner deposited c-Sifilms also reducing the finished solar module energy payback time toless than 1 to 2 years. Manufacturing cost is further reduced byeliminating wire sawing and related kerf losses associated withmainstream solar cell wafer manufacturing technology. Manufacturing costis still further reduced by using self-aligned processing without anylithography or patterning steps used during the substrate and cellfabrication process flow, and a reduced number of fabrication processsteps, with improved yield and cycle time. Production cost is stillfurther reduced by using a simplified interconnection and cell-moduleassembly process and lightweight monolithic modules.

Operational reliability is improved by using thinner silicon films,eliminating photo-degradation and reducing temperature coefficients.Operational reliability is further improved by using a simpledistributed high-conductance electrical interconnection, minimizingfield failures. Operational reliability is still further improved byeliminating module glass cover (for glassless module assembly), thusreducing cost and facilitating field installation and operation.Operational reliability is still further improved by reducing the numberof manufacturing process steps and process variations using in-linemanufacturing process control.

The current disclosure reduces the solar module cost per watt for theuser (by at least 30% to 50%) and cuts balance-of-system (BOS) andinstallation costs for the integrators and installers. This may offermajor benefits to the global grid-tied end-users and solar systeminstallers and integrators. The current disclosure reduces the moduleintegration and installation cost and installed solar cell system costper W_(p) for the user, thereby lowering finished system cost per W_(p).The current disclosure increases module efficiency, with higher moduleefficiency resulting in lower BOS cost. The lower installed solar cellsystem cost results in reduction of the economic break-even time to alower fraction of the system lifetime, from roughly ½ to ⅓ for currentbest-of-breed c-Si solar cell systems to less than ¼ to ⅛ for theembodiments of this disclosure. The current disclosure reduces energypay-back time (EPBT) from 3 to 7 years for best-of-breed c-Si solar cellsystems to less than 1 to 2 years for the embodiments of thisdisclosure. Reduced EPBT substantially increases the net lifetime energyoutput (in kWh) for field-installed modules. The cell designs and moduleassemblies of this disclosure also provide stable degradation-free fieldoperation over an extended time (e.g., 30 to 40 year life of themodule), further increasing the net lifetime electrical energy output.Module manufacturing costs are expected to be 30% to 65% lower than thatof the leading high-performance c-Si solar cells/modules at the time ofmarket entry. This may shorten the ROI break-even time for the userscompared to the current industry roadmap and projections. Furtherbenefits include increased field performance stability and reliabilityand reduced environmental impact (non-toxic materials and shortenedEPBT). Further, the cell and module designs of this disclosure are idealfor grid-tied applications where it is advantageous to maximizeelectricity generation from a limited building rooftop or façade area.

The absorber silicon film thickness of the current disclosure may be avalue in the range of roughly 1 to 30-microns, where a thinner siliconlayer is preferred for less material consumption (in one embodiment, inthe range of 1 to 10 microns). Even after taking into account theeffective surface area increase due to the 3-D geometric structure ofthe 3-D TFSC substrates, the 3-D TFSC substrates of this disclosureconsume substantially less silicon material than the state-of-the-artwafer-based c-Si solar cells. Moreover, there are no sawing or kerflosses. Similarly, there is no requirement for saw damage removal sincethe 3-D crystalline silicon film is process-ready upon release from thereusable template. This substantially reduces the solar cell costassociated with silicon consumption. The self-supporting 3-D epitaxialsilicon thin film is deposited on and released from a low-cost reusablecrystalline (monocrystalline or multicrystalline) silicon substrate(template). The template may be reused numerous times before beingreconditioned or recycled. The template may even be chosen from the muchlower cost metallurgical-grade c-Si since any metallic impurities areprevented from contaminating the 3-D crystalline silicon film.

FIG. 3 summarizes the overall crystalline solar cell fabrication processflow of prior art techniques and highlights the specific stepseliminated by the current disclosure, compared to the prior art. FIG. 4summarizes the overall cell and module fabrication process flow and thecompetitive advantages of the current disclosure, compared to the priorart. As highlighted here, the current disclosure enables fabrication of3-D thin-film solar TFSC substrates and cells, thus, substantiallyreducing consumption of semiconductor absorber material (e.g., silicon)and the cell and module manufacturing costs. FIG. 5 provides anothersummary of the benefits of the embodiments of the current disclosure.

The 3-D TFSCs of the disclosed subject matter utilize a 3-D TFSCsubstrate which has a plurality of unit cell cavities to capture andsubstantially trap solar light on the substrate frontside, while thesubstrate backside includes a continuous thin semiconductor layer whichis attached to the rear sides of the unit cell cavities.

FIG. 6 shows a top view 100 of a hexagonal-prism 3-D TFSC with aperipheral planar silicon frame 102. The top surface of the frame 102may also be used as the top 3-D TFSC interconnect and may be used toproduce a wrap-through or wrap-around emitter metallization for makingcontacts to the cell emitter at the bottom of the cell (in moduleassembly). The frame 102 is metallized, along with the top hexagonalemitter contacts, and is electrically connected to the hexagonal emittercontacts. The frame 102 may have the same thickness as the 3-D TFSCsubstrate or may be much thicker. In one embodiment, frame width 104 isbetween 5 and 500 microns. The hexagonal prism 3-D TFSC substrate iscomposed of hexagonal-prism unit cells 106. In one embodiment, the width108 of the silicon film forming the sidewalls of the hexagonal prismunit cell is preferably 2 to 30 microns, and more preferably 2 to 10microns. Typically, there are thousands to millions of hexagonal-prismunit cells 106 on a large-area 3-D TFSC. In one embodiment, frame length(S) 110 ranges from 125 to over 200 millimeters (e.g., 210 mm×210 mm).The hexagonal-prism 3-D TFSC substrates of this disclosure may have athin silicon frame, a thick silicon frame, or no peripheral frame atall.

FIGS. 7A and 7B show microscopic views of 3-D TFSC substrates of a 3-DTFSC as illustrated in FIG. 6. FIG. 7A shows a view of a dual-apertureTFSC substrate without a base layer whereas FIG. 7B shows a view of asingle-aperture TFSC substrate with a base layer.

FIG. 8 provides an overview of the 3-D TFSC substrate and cellfabrication process flow. Focusing on the top of FIG. 8 illustrating the3-D TFSC substrate fabrication, note that the first step in this processflow uses a pre-fabricated template. The template with a pre-fabricated3-D trench or groove pattern may be used for formation of 3-D TFSCsubstrates, which are then used in the formation of 3-D TFSCs,substantially eliminating or reducing disadvantages and problemsassociated with previously developed TFSCs and the wafer-basedcrystalline silicon cell technologies. The template is capable of beingused numerous times (e.g., tens to hundreds of times) to fabricatenumerous 3-D TFSC substrates before being reconditioned or recycled. Inone embodiment, the template may be used hundreds of times to fabricate3-D TFSC substrates before being recycled. The template may be reusedfor as long as it remains relatively free of dislocations and/or for aslong as it maintains an acceptable trench or groove pattern with widthsand surface conditions within acceptable control limits (e.g., as gaugedby in-line metrology).

FIG. 4 shows a view 120 of a template with hexagonal-prism posts(pillars) 122. A hexagonal-prism 3-D TFSC substrate (not shown) isfabricated by first forming a suitable relatively conformal thinsacrificial layer (in one embodiment, porous silicon) on the template,then filling in the relatively deep trenches 124 between hexagonal-prismposts 122, and subsequently releasing the hexagonal prism 3-D TFSCsubstrate by selectively etching the sacrificial layer (not shown)deposited between the hexagonal-prism 3-D TFSC substrate and thetemplate. In one embodiment, the template has deep interconnectedhexagonal-prism trenches with slightly tapered sidewalls (i.e., largertrench widths near the top of the trenched compared to near the bottomof the trenches. Moreover, the trench widths near the top of thetrenches may be made about one to several microns larger than the trenchwidths near the bottom of the trenches. FIGS. 10A and 10B show magnifiedviews of one embodiment of a template with hexagonal-prism posts 122 andtrenches 124. This embodiment was prepared using photolithography anddeep reactive-ion etching (DRIE).

Note that the terms “honeycomb” and “hexagonal” are used interchangeablythroughout this disclosure. The term “honeycomb” refers to the fact thatembodiments of the 3-D TFSC substrates resemble a natural honeycomb.

FIG. 11 shows a view 130 of an alternative embodiment of a template (ormaster stencil) with staggered square prism posts 132. A square-prism3-D TFSC substrate (not shown) is formed by first depositing or forminga relatively conformal sacrificial layer (e.g., porous silicon), fillingin the trenches 134 between square prism posts 132, and subsequentlyreleasing the 3-D TFSC substrate by selectively etching the sacrificiallayer formed between the 3-D TFSC substrate and the template.

FIG. 12 shows a schematic view 140 of a hexagonal-prism single-aperture142 3-D TFSC substrate with prism sidewalls 144, with thehexagonal-prism 3-D TFSC substrate rear side 146 monolithicallyconnected to a relatively flat planar thin film 148 (rear base layer).

FIG. 13 shows a schematic magnified top view 150 of a regular(equilateral) hexagonal-prism 3-D TFSC substrate showing a plurality ofprism unit cells. Each hexagonal unit cell 106 contains hexagonal unitcell boundary points (H₁, H₂, H₃, H₄, H₅, and H₆) 152, 154, 156, 158,160, 162. FIG. 13 shows the hexagonal-prism 3-D TFSC substrate sidewalls144; the long diagonal dimension of the unit cell hexagon (d) 164; andthe short diagonal dimension of the hexagonal unit cell (h) 166. In oneembodiment, the hexagonal-prism 3-D TFSC substrate sidewalls 144 arebetween 2 and 30 microns thick.

FIG. 14A shows a Y-Y cross-sectional view 170 of the hexagonal-prismsingle-aperture 3-D TFSC substrate with a rear base layer shown in FIG.12. FIG. 14B shows a Z-Z cross-sectional view 180 of the hexagonal-prism3-D TFSC substrate shown in FIG. 12. These FIGURES also show thehexagonal thin silicon walls 144 monolithically attached to the rearbase layer 148. Note that the 3-D TFSC substrate has height 172 in bothFIGUREs.

FIGS. 15 through 20 show six different process flow embodiments of thisdisclosure for fabricating single-aperture hexagonal-prism 3-D TFSCswith rear base layers. While these process flow embodiments are outlinedfor fabricating silicon-based TFSCs, the overall concepts andmethodologies may be extended and applied to other homojunction andheterojunction semiconductor materials (such as multicrystallinesilicon, polycrystalline silicon, CIGS, etc.). While the process flowsshown are for fabrication of 3-D c-Si TFSCs, the embodiments may beeasily adjusted and modified to fabricate silicon-based TFSCs usingpolysilicon, amorphous silicon, and/or multicrystalline silicon films.

FIGS. 15 through 20 show six different process flow embodiments 190,220, 250, 280, 310, and 340 of this disclosure for fabrication ofsingle-aperture hexagonal-prism 3-D TFSCs with rear base layers (i.e.,the honeycomb-prism structures have a monolithically attached thin baselayer). These embodiments may use one of the templates described andshown previously. These TFSC substrates may be fabricated usingtemplates with trenches with shallow wider trenches (shoulders) on topof deeper narrower trenches (or using deep trenches with flared outregions on top of the trenches, that is, trench widths larger on the topof the deep trenches compared to the trench widths in the lower sectionsof the deep trenches). These six embodiments all result insingle-aperture hexagonal-prism 3-D TFSCs with self-aligned selectiveemitter and base diffusion regions in silicon as well as self-alignedemitter and base contact metallization regions. While shown forcrystalline silicon (c-Si) cells, the methodologies of these embodimentsmay also be extended and applied to polysilicon/amorphous silicon aswell as non-Si TFSCs. These embodiments include either detached rearmirrors (for instance, mirrors provided by silver-coated copper orsilver-coated aluminum pads on solar module printed-circuit boards) orpreferably integrated/attached rear mirrors deposited directly on therear surface of the cell passivation dielectric (e.g., on thermal oxide)layer on the rear base layer. Both the detached and integrated/attachedmirrors may also serve as the base interconnect planes (electricallyconnected to the hexagonal base contact metallization). In oneembodiment, the material for a high-reflectivity mirror is silver(alternatively, aluminum may be used).

FIG. 15 shows a process flow 190 for fabrication of single-aperturehexagonal-prism 3-D TFSCs with rear base layers using self-alignedselective plating metallization with boron-doped p⁺⁺ rear base contactsby selective base doping (besides selective emitter doping). Thishexagonal-prism 3-D TFSC with rear base layer uses a detached rearmirror (i.e., rear mirror is not an integrated layer directly depositedon the rear base layer). In step 192, cell processing starts with asingle-crystal (or multicrystalline or polycrystalline) p-type (forn-type selective emitter), 3-D silicon TFSC substrate (e.g., a 3-D arrayof honeycomb hexagonal prisms). As with any other cells in thisdisclosure, the substrate doping polarity may be changed to n-type (forp-type selective emitter). The 3-D honeycomb prism TFSC substrate hasopen top apertures and no rear apertures (due to the rear base layer).There is a rear relatively flat base silicon layer monolithically andintegrally attached to the honeycomb-prism cell. Step 194 involvesselectively coating the top ridges of the 3-D honeycomb prisms (in oneembodiment, the top 2 to 10 microns) with an n-type dopant source. Inone embodiment, this n-type dopant source is phosphorus. Selectivecoating may be done by self-aligned roller coating using paste/liquidsource, liquid-dip coating by dipping in a known liquid source depth,ink-jet coating, or spray coating. Next, the n-type dopant source layeris dried and cured (e.g., by thermal curing at 250° C. to 400° C. or UVirradiation). Step 196 involves selectively filling the rear basetroughs on the substrate backside with a p-type liquid/paste dopantsource layer. In one embodiment, the p-type dopant source is boron.Selective filling may be done by boron source layer coating (e.g.,roller, spin-on, ink-jet, or spray coating) followed by selectiveetch-back (e.g., by solvent spin-on) to form filled troughs. Next, thep-type dopant source layer is dried and cured (e.g., by thermal curingat 250° C. to 400° C. or UV exposure). Step 198 involves formingself-aligned selective emitter and base regions. The top n⁺⁺p emitterdiffusion contact, top aperture n⁺p selective emitter junctions, rearp⁺⁺ base contacts and selectively doped p⁺base regions (the latter areoptional) are concurrently formed. This may be done using thermal annealin a diffusion furnace at 800° C. to 950° C. In one embodiment, the 3-DTFSC substrate is annealed while placed in an in-line diffusion furnace,or with stacks of 3-D TFSC substrates in face-to-face contact tofacilitate vapor-phase doping formation of n⁺ emitter and p⁺ base. Step200 involves surface passivation (oxidation), where a thermal oxidelayer is grown, in one embodiment by steam oxidation (e.g., 10 to 200nanometers at 800° C. to 950° C.). Step 200 may be merged into the priordiffusion step in multi-zone furnace, to be performed sequentially afterthe selective emitter and base diffusion step. In one embodiment, thediffusion/oxidation steps result in selective emitter and emittercontact sheet resistance values of 80-150 Ω/square and 10-70 Ω/square,respectively. Step 202 involves selective etching of the cured layers inpreparation for self-aligned metallization. The dopant source layers areselectively etched (i.e., the n-type coating on top honeycomb prismridges and the p-type coating in rear filled troughs) with a suitabledielectric etchant (e.g., an HF-based etchant) with high selectivitywith respect to thermal oxide. This selectively strips the cured dopedand undoped dielectrics on the top and rear portions of the substrateand exposes silicon in those regions, while removing only a smallfraction of thermal oxide from other 3-D TFSC substrate regions. Step204 involves self-aligned metallization (in one embodiment, by plating).The front and rear emitter and base metallized regions are concurrentlyformed using selective electroplating and/or electroless plating and/orgalvanic plating to form single or multilayer high-conductivitymetallized regions (silver, aluminum, nickel, titanium, cobalt,tantalum). For instance, the plated metal stack may include a thin (50to 500 nanometers) barrier and adhesion layer such as nickel (nickel)followed by a relatively thick (2 to 15 microns) layer ofhigh-conductivity metal (silver or copper or aluminum). If ahigh-conductivity metal other than silver is used for the thickmetallization layer, a final flash coat of silver may be used to createa high-reflectivity surface coating in order to improve light reflectionand trapping into the 3-D cells (by the emitter metallization contact).Step 206 involves an optional forming-gas anneal. A forming gas annealmay be performed (e.g., 350° C. to 450° C.) to reduce front and rearinterconnect resistance values and help with surface/bulk passivation.Step 208 involves mounting honeycomb prism TFSC rear side (base side)onto a highly reflective (diffuse with a rough surface or specular witha smooth surface) rear mirror. This rear mirror may be made of ansilver-coated aluminum or copper foil and may also serve as the TFSCbase interconnect plane on a printed-circuit board (PCB) in a solarmodule. Step 210 involves an optional step of depositing a passivationand ARC layer on mounted cells. In one embodiment, this passivation andARC layer is PVD or PECVD SiN_(x) with thickness between 50 and 200nanometers. Step 212 involves proceeding with packaging the honeycombprism TFSCs in solar module assembly.

FIG. 16 shows an alternative process flow 220 for fabrication ofsingle-aperture hexagonal-prism 3-D TFSCs with rear base layers usingself-aligned selective plating metallization without boron-doped p⁺⁺rear base contacts by selective base doping. The p⁺⁺ base contact dopingis performed by aluminum doping using aluminum from base contactmetallization and an anneal (contact firing process). As in FIG. 15,this process flow uses cured phosphorus source layer and a thermalanneal to form the n⁺ phosphorus-doped selective emitter regions and then⁺⁺ phosphorus-doped emitter contact diffusion regions. Thissingle-aperture hexagonal-prism 3-D TFSC with rear base layer also usesa detached rear mirror (i.e., rear mirror is not an integrated layerdirectly deposited on the rear base layer). Step 222 (providing asubstrate) corresponds to step 192 of FIG. 128; and step 224 (selectivecoating) corresponds to step 194. Step 226 (selective filling) involvesselectively filling the rear base troughs on the TFSC substrate backsidewith an undoped sealant dielectric (e.g., oxide and/or nitride) using adielectric liquid/paste source layer. Selective filling may be done byundoped dielectric source layer coating (e.g., roller, spin-on, ink-jet,or spray coating) followed by selective etch-back (e.g., by solventspin-on) to form filled troughs. Next, the undoped dielectric sourcelayer is dried and cured (e.g., by thermal curing at 250° C. to 400° C.or UV exposure). Step 228 involves self-aligned selective emitter andbase. The top n⁺⁺p emitter contact and honeycomb top apertures n+pselective emitter junctions are concurrently formed using thermal annealat 800° C. to 950° C. In one embodiment, the 3-D TFSC substrate may beannealed while placed in an in-line diffusion furnace, or with stacks of3-D TFSC substrates in face-to-face contact to facilitate vapor-phasedoping formation of n+p selective emitter and n⁺⁺p emitter contactregions. Step 230 (surface passivation oxidation) corresponds to step200 of FIG. 15. Step 232 involves selective etching of the cured layersin preparation for self-aligned metallization. The dopant source layer(i.e., the n-type coating on top honeycomb prism ridges) and the undopeddielectric filling in rear filled troughs) are selectively etched with asuitable etchant (e.g., an HF etchant) with high selectivity withrespect to thermal oxide. This selectively strips the cured dopantsource dielectrics on the top and rear portions of the 3-D TFSCsubstrate and exposes silicon in those regions, while removing only asmall fraction of thermal oxide from other 3-D TFSC substrate regions.Step 234 involves self-aligned metallization (embodiments includeelectroless plating, galvanic plating, and/or electroplating). The rearbase aluminum metallized regions are selectively formed by selectiveelectroplating or electroless plating. In one embodiment, this aluminumplating process limited to the rear base regions. Step 236 involves ananneal or firing process to form rear aluminum-doped p⁺ contacts. Anoptional forming gas anneal (e.g., 350° C. to 450° C.) is performed toreduce interconnect resistance and help with surface/bulk passivation.Step 238 involves self-aligned metallization (plating). A suitablehigh-conductivity metal such as silver or copper (e.g., 2 to 12 microns)is selectively/concurrently deposited on the top honeycomb ridges(emitter) and rear aluminum-filled troughs (aluminum metallized basecontacts) by plating. If necessary, the plating process may firstinvolve selective deposition of a suitable refractory metal barrier andadhesion layer (e.g., 50 to 200 nanometers nickel) followed by thedeposition of the thicker higher conductivity metal (silver and/orcopper). If necessary, the metallized regions are then flash coated witha thin layer of silver in order to establish a high optical/IRreflectivity (this step may be merged into the prior plating step). Ifsilver is used as the main metallization layer, then the top solverflash coating may not be needed. Step 240 (mounting) corresponds to step208 of FIG. 15; step 242 (ARC layer) corresponds to step 210; and step244 (proceeding with packaging) corresponds to step 212.

FIG. 17 shows another alternative process flow 250 for fabrication ofhexagonal prism 3-D TFSCs with rear base layers using self-alignedselective plating metallization with boron-doped p⁺⁺ rear base contactsby selective base doping (besides selective emitter doping). Thissingle-aperture hexagonal-prism 3-D TFSC with rear base layer uses anintegrated rear mirror which is directly deposited (e.g., silver oraluminum formed by sputtering, evaporation, or another method such asnon-selective plating) on the rear base passivation dielectric layer(the rear base passivation layer may be a thermal oxide layer).Optionally, the rear base passivation dielectric (e.g., oxide) layersurface may be treated (e.g., with plasma) to produce a rough dielectricsurface (e.g., with an RMS surface roughness in the range of tens tohundreds of nanometers) prior to mirror layer deposition. This mayproduce a diffuse integrated mirror directly on the rear surface of therear base layer passivation layer. Alternatively, the TFSC substrate mayalready be textured as a result of using a textured template, resultingin a diffuse rear mirror.

Step 252 (providing a substrate) corresponds to step 222 of FIG. 16; andstep 254 (selective coating) corresponds to step 224. Step 256 involvesselectively filling the rear base troughs on the 3-D TFSC substratebackside with p-type (e.g., boron) liquid/paste dopant source. This maybe done by boron source layer coating (e.g., roller, spin-on, ink-jet,or spray coating) followed by etch-back (e.g., by solvent spin-on) toform filled troughs. The layer is then dried and cured (using thermalcuring at 250° C. to 400° C. or UV exposure). Step 258 involvesself-aligned selective emitter and base. The top n⁺⁺p emitter contact,honeycomb top apertures n+p selective emitter junctions, the rear p⁺⁺base contact and selectively doped p⁺ base regions are concurrentlyformed using thermal anneal at 800° C. to 950° C. In one embodiment, the3-D TFSC substrate is annealed while placed in an in-line diffusionfurnace, or with stacks of 3-D TFSC substrates in face-to-face contactto facilitate vapor-phase doping formation of n⁺ emitter and p⁺ base.Step 260 (surface passivation oxide) corresponds to step 230 of FIG. 16.Step 262 involves selective etching of the cured layers in preparationfor self-aligned metallization. The dopant source layers (i.e., then-type coating on top honeycomb prism ridges and the p-type coating inrear filled troughs) are selectively etched with a suitable dielectricetchant (e.g., an HF-based etchant) with a relatively high selectivitywith respect to thermal oxide. This selectively strips the cured dopantlayers on the top and rear portions of the 3-D TFSC substrate andexposes silicon in those regions, while removing only a small fractionof thermal oxide from other 3-D TFSC substrate regions (e.g., thermaloxide coating remains on all selective emitter regions and rear basebackside regions outside the base contact area). Step 264 involves anoptional plasma treatment step. A plasma treatment process may beperformed to roughen the thermal oxide layer on the substrate backside(for integrated diffuse rear mirror). Step 266 involves self-alignedmetallization (plating). The front and rear emitter and base metallizedregions are concurrently formed using selective electroplating and/orelectroless plating and/or galvanic plating to form single or multilayerhigh-conductivity metallized regions (silver, aluminum, nickel,titanium, cobalt, tantalum). For instance, the plated metal stack mayinclude a thin (50 to 500 nanometers) barrier and adhesion layer such asnickel (nickel) followed by a relatively thick (2 to 15 microns) layerof high-conductivity metal (silver or copper or aluminum). If ahigh-conductivity metal other than silver is used for the thickmetallization layer, a final flash coat of silver may be used to createa high-reflectivity surface coating in order to improve light reflectionand trapping into the 3-D cells (by the emitter metallization contact).Step 268 involves an optional forming gas anneal step is (e.g.,performed at 350° C. to 450° C.) to reduce front and rear interconnectresistance values and help with surface/bulk passivation. Step 270involves addition of an integrated rear cell mirror. A thin (e.g., 50 to1000 nanometers) layer of high-reflectance metal (silver and/oraluminum, among others) is deposited on TFSC substrate backside (e.g.,by PVD, non-selective plating, or evaporation). This thin layer alsoserves as base interconnect plane. Step 272 involves an optional step ofdepositing an ARC (e.g., 50 to 200 nanometers PVD or PECVD hydrogenatedSiN_(x) or AlO_(x)) layer on substrate frontside. This step is may beperformed either before or after mounting the cells in the moduleassembly. Step 274 (proceeding with packaging) corresponds to step 244of FIG. 16.

FIG. 18 shows another alternative process flow 280 for fabrication ofsingle-aperture hexagonal-prism 3-D TFSCs with rear base layers usingself-aligned selective plating metallization without boron-doped p⁺⁺rear base contacts by selective base doping. The p⁺⁺ base contact dopingis performed by aluminum doping (aluminum contact firing) using aluminumfrom base contact metallization and an anneal (firing process). Thisprocess flow uses cured phosphorus source layer and a thermal anneal toform the n⁺ phosphorus-doped selective emitter regions and the n⁺⁺phosphorus-doped emitter contact regions (the latter underneath thecured phosphorus doping layer). This single-aperture hexagonal-prism 3-DTFSC with rear base layer uses an integrated rear mirror which isdirectly deposited (embodiments include silver and/or aluminum depositedby PVD, evaporation, or non-selective plating) on the rear basepassivation dielectric layer. As an option, the rear base passivationdielectric (e.g., oxide) layer surface may be treated (e.g., withplasma) to produce a roughened dielectric surface (e.g., with an RMSsurface roughness of roughly tens to hundreds of nanometers) prior tomirror layer deposition. This produces a diffuse integrated mirrordirectly on the rear surface of the rear base layer passivation layer.Alternatively, the TFSC substrate rear base layer may be pre-textured bya textured template surface (thus, eliminating the need for such plasmatreatment). Step 282 (providing a substrate) corresponds to step 252 ofFIG. 17; and step 284 (selective coating) corresponds to step 254. Step286 (selective filling) corresponds to step 226 of FIG. 16; step 288(self-aligned selective emitter and base) corresponds to step 228 ofFIG. 16; step 290 (surface passivation) corresponds to step 230 of FIG.16; and step 292 (etch) corresponds to step 232 of FIG. 16. Step 294(optional plasma treatment step as part of self-aligned metallization)corresponds to step 264 of FIG. 17. Step 296 (plating) corresponds tostep 234 of FIG. 16; step 298 (anneal) corresponds to step 236 of FIG.16; and step 300 (plating) corresponds to step 238 of FIG. 16. Step 302(integrated mirror) corresponds to step 260 of FIG. 17; step 304 (ARClayer) corresponds to step 262 of FIG. 17; and step 306 (proceeding withpackaging) corresponds to step 264 of FIG. 17.

FIG. 19 shows another alternative process flow 310 for fabrication ofsingle-aperture hexagonal-prism 3-D TFSCs with rear base layers usingself-aligned fire-through metallization with boron-doped p⁺⁺ rear basecontacts by selective base doping (besides selective emitter doping).This hexagonal-prism 3-D TFSC with rear base layer uses a detached rearmirror in module assembly (i.e., rear mirror is not an integrated layerdirectly deposited on the rear base layer). Step 312 (providing asubstrate) corresponds to step 252 of FIG. 17; step 314 (selectivecoating) corresponds to step 254; step 316 (selective filling)corresponds to step 256; and step 318 (self-aligned selective emitterand base) corresponds to step 258. Step 320 involves formation ofsurface passivation and ARC. The top (emitter phosphorus) dopant sourcelayer, rear (base boron) dopant source layer, and any native oxide arestripped using a suitable etchant (e.g., using HF etchant). A thin oxidelayer (e.g., 5 to 100 nanometers) is grown by steam oxidation (e.g., 3to 300 nanometers at 800° C. to 950° C.). This thermal oxidation step isoptional. Next, an ARC layer (e.g., 3 to 100 nanometers hydrogenatedSiN_(x)) is deposited by PECVD or PVD, with passivation layer formed onprism top and sidewalls (coverage on the cell rear is optional). ThePECVD or PVD SiN_(x) (or AlO_(x)) also provides H passivation of the 3-DTFSC substrate. In one embodiment, the diffusion/oxidation steps resultin selective emitter and emitter contact diffusion sheet resistancevalues of 80-150 Ω/square and 10-70 Ω/square, respectively. Step 322involves self-aligned metallization (metal coat). The top portions ofthe honeycomb prisms are selectively coated (to a height equal to orless than the dopant source layer) with metal (in one embodiment,silver) liquid or paste using self-aligned roller, inkjet, liquid dip,or spray coating. Next, this layer is dried and cured (250° C. to 400°C. or UV). The rear base troughs on the substrate backside are thenselectively filled with metal liquid or paste (silver and/or aluminum).This may be done by roller, spin-on, ink-jet, or spray coating followedby etch-back (e.g., by solvent spin-on or selective cell backsideetchback) to form filled troughs. This layer is then dried and cured(250° C. to 400° C. or UV). Step 324 involves self-aligned metallization(fire-through). The cell front (silver) and rear (aluminum and/orsilver) metallized regions are formed by firing through the oxide/PECVD(or PVD) SiN_(x) layers. Step 326 involves an optional self-alignedplating metallization step. A layer of silver or copper (e.g., roughly 1to 5 microns) is selectively/concurrently deposited on the metallizedtop honeycomb ridges (emitter) and rear honeycomb ridges (base) byplating. If necessary, a refractory metal barrier layer such as nickelmay be deposited by plating before copper or silver plating. Next, themetallized regions are flash coated with silver. Step 328 (optional FGA)corresponds to step 268 of FIG. 17. Step 330 (mounting) corresponds tostep 240 of FIG. 16. Step 332 (proceeding with packaging) corresponds tostep 306 of FIG. 18.

FIG. 20 shows another alternative process flow 340 for fabrication ofsingle-aperture hexagonal-prism 3-D TFSCs with rear base layers usingself-aligned fire-through metallization and with boron-doped p⁺⁺ rearbase contacts formed by selective base doping (besides selective emitterdoping). This hexagonal-prism 3-D TFSC with rear base layer uses anintegrated (attached) rear mirror which is directly deposited (e.g.,silver or aluminum by PVD or evaporation or non-selective plating) onthe rear base passivation dielectric layer. As an option, the rear basepassivation dielectric (e.g., oxide) layer surface may be treated (e.g.,with plasma) to produce a rough dielectric surface (e.g., with an RMSsurface roughness of roughly tens to hundreds of nanometers) prior tomirror layer deposition. This may produce a diffuse integrated mirrordirectly on the rear surface of the rear base layer passivation layer.Alternatively, a textured TFSC substrate base layer may be formed byusing a textured template (thus, eliminating the need for an optionalplasma treatment step). Step 342 (providing a substrate) corresponds tostep 312 of FIG. 19; step 344 (selective coating) corresponds to step314; step 346 (selective filling) corresponds to step 316; step 348(self-aligned emitter and base) corresponds to step 318; and step 350(surface passivation and ARC) corresponds to step 320. Step 352 involvesan optional plasma treatment step to roughen the thermal oxide layer onthe substrate backside (for integrated diffuse rear mirror). Step 354(metal coat) corresponds to step 322 of FIG. 19; step 356 (fire-through)corresponds to step 324; step 358 (optional FGA) corresponds to step328; and step 360 (plating) corresponds to step 326. The plating and FGAprocess steps are reversed. Step 362 (integrated mirror) corresponds tostep 302 of FIG. 18; and step 364 (proceeding with packaging)corresponds to step 306.

In regard to the n-type (e.g., phosphorus) dopant liquid/paste coveringthe top portion of the hexagonal ridges, a single furnace anneal processin a diffusion furnace (e.g., at roughly 800° C. to 950° C.) producesmore heavily-doped regions with higher surface phosphorus concentrationson the top silicon hexagonal ridges directly in contact with andunderneath the cured n-type dopant solid source layer compared to otherregions not covered with the cured dopant source layer. The TFSCsubstrates may be processed with the emitter side facing down through anin-line diffusion furnace. Through vapor-phase transport of thevaporized dopant source to the adjacent frontside regions within thehexagonal prism unit cell cavities, the furnace anneal concurrentlydopes the remaining frontside surface regions not covered with the soliddopant source layer with phosphorus with smaller surface concentration(e.g., 1×10¹⁹ to 5×10¹⁹ cm⁻³), thus, creating self-aligned selectiveemitter regions. These less heavily doped regions with higher sheetresistance values (in one embodiment, in the range of 100 Ω/square to150 Ω/square) improve the blue response of the 3-D TFSC, while the moreheavily doped honeycomb ridges may minimize the frontside emittercontact resistance of the 3-D TFSC. Similarly, the same furnace annealprocess produces more heavily doped p⁺-doped hexagonal prism diffusedbased contacts for low base contact resistance. For hexagonal-prism 3-DTFSCs with rear base layers, the remaining rear base layer rear surfacebase regions are less heavily doped on the surface, resulting inselective base doping (and a back-surface field or BSF region).

The above process steps may be performed on integrated in-line processequipment. For example, FIG. 21 shows a view 400 of a setup forperforming the two process steps of liquid/paste coating and UV or IRcuring prior to furnace anneal, allowing for subsequent formation ofselective emitter and base regions after anneal in an in-line diffusionfurnace. This integrated in-line process equipment allows forself-aligned formation of dopant liquid or paste coating on the 3-D TFSCsubstrate hexagonal-prism top ridges and hexagonal-prism rear ridges byroller coating. Roller coating may be performed using anatmospheric-pressure, belt-driven coating and curing equipmentintegrated in line with a diffusion furnace. In one embodiment, the topridges are coated with n-type dopant liquid/paste; the rear ridges arecoated with p-type dopant liquid/paste.

The 3-D TFSC substrate 402 is shown moving in 404 on input conveyor belt406. The rotating top rollers 408, with top roller pads 410, apply acontrolled downward force to coat the top hexagonal prism ridges withn-type paste. The rotating rear rollers 412, with rear roller pads 414,apply a controlled upward force to coat the rear hexagonal prism ridgeswith p-type paste. Multilayer materials may be coated on each side ofthe 3-D TFSC substrate by applying (or flowing) a different liquid orpaste material to each roller on the top 408 and/or rear 410 set ofrollers. The 3-D TFSC substrate 402 next moves into the curing areawhere the dopant liquid/paste layers are concurrently formed using acuring lamp 416 which uses IR or UV curing beams 418. The 3-D TFSCsubstrate 402 is next shown moving out 420 to the output conveyor belt422, which may move the substrate 402 to an in-line diffusion furnace,where the n⁺ and p⁺ contacts and selective emitter regions areconcurrently formed.

A similar roller coater setup may be properly configured and used forapplying metal liquid/paste coatings (e.g., silver and/or aluminumliquid or paste sources), curing the metal liquid/paste source, andperforming subsequent thermal anneal in an in-line atmospheric furnace(resistively-heated or lam-heated furnace) for fire-throughmetallization in order to form the emitter and base contactmetallization (and whenever applicable, also to form the aluminum-dopedp⁺⁺ base contact regions).

FIG. 22 shows a view 430 of an alternative setup design to perform thesame processes as the roller coater/curing/furnace setup of FIG. 21. Thesetup in FIG. 22 may be used for self-aligned formation of dopant sourceliquid/paste coating on the 3-D TFSC substrate top ridges andhexagonal-prism rear ridges by angled spray coating. This setup also mayutilize an in-line atmospheric-pressure coating and curing and diffusionequipment configuration which can be easily integrated with an in-linediffusion furnace. As with the roller coater setup in FIG. 21,multilayer materials may be coated on each side of the substrate byusing multiple sets of spray nozzles connected to different liquidsources (not shown here) and applying (or flowing) a different liquidsource material to each nozzle on the top and/or rear set of spraynozzles. This is an alternative technique to the roller coating systemshown in FIG. 21. In one embodiment, the top ridges are coated withn-type dopant liquid/paste (such as phosphorus); the rear ridges arecoated with p-type dopant liquid/paste (such as boron). Referring toFIG. 22, the 3-D TFSC substrate 402 is shown moving in 404 on inputconveyor belt 406. Angled nozzles 432 spray n-type dopant liquid ontothe surface at a sharp angle with respect to the surface (nozzles coverwafer width). This n-type dopant liquid comes from an n-type liquiddopant source and nozzle reservoir/pump 434. Angled nozzles 436 sprayp-type dopant liquid onto the surface at a sharp angle with respect tothe surface (nozzles cover wafer width). This p-type dopant liquid comesfrom a p-type liquid dopant source and nozzle pump 438. The 3-D TFSCsubstrate 402 next moves into the curing area where the dopantliquid/paste layers are concurrently formed using a curing lamp 416which uses IR or UV curing beams 418. The 3-D TFSC substrate 402 is nextshown moving out 420 to the output conveyor belt 422, which may move thesubstrate 402 to an in-line diffusion furnace, where the n⁺ and p⁺contacts and selective emitter regions are concurrently formed.

The angled spray technique limits the vertical height of theliquid/paste coating to a portion of the hexagonal ridges and preventsthe liquid source from coating the inner parts of the hexagonal prismcavity sidewalls and/or rears. This type of in-line (or another drivemethod) processing system may also be used for applying metal sourceliquid (e.g., silver and/or aluminum source liquid) for fire-throughmetallization applications as well as applying liquid etchant forselective etching of dielectrics (e.g., oxide and/or solid dopant sourcelayer) from the top and/or rear hexagonal prism ridges.

FIG. 23 shows a view 440 of another alternative setup to perform thesame processes as the in-line roller coater/curing setup of FIG. 21 andthe in-line spray coater/curing setup of FIG. 22. The setup in FIG. 23may be used for self-aligned formation of dopant liquid/paste coating onthe 3-D TFSC substrate hexagonal top ridges and hexagonal prism rearridges by liquid-dip coating. This setup also may utilize an in-lineatmospheric-pressure coating and curing equipment configuration to beattached to the input stage of an in-line diffusion (or fire-through)furnace.

In one embodiment, the top ridges are coated with n-type dopantliquid/paste (such as phosphorus); the rear ridges are coated withp-type dopant liquid/paste (such as boron). The 3-D TFSC substrate 402is shown moving in 404 on input conveyor belt 406. Liquid film dispensercontaining n-type liquid dopant source 422 applies a controlledthickness n-type liquid dopant film 444. This n-type dopant liquid comesfrom n-type liquid dopant source and liquid level and depth controller446. Liquid film dispenser containing p-Type liquid dopant source (withperipheral air levitation) 448 applies a controlled thickness p-typeliquid dopant film 450. This p-type dopant liquid comes from p-typeliquid dopant source and liquid level and depth controller 452. The 3-DTFSC substrate 402 next moves into the curing area where the dopantliquid/paste layers are concurrently formed using a curing lamp 416which uses IR or UV curing beams 418. The 3-D TFSC substrate 402 is nextshown moving out 420 to the output conveyor belt 422, which may move thesubstrate 402 to an in-line diffusion furnace, where the n⁺ and p⁺contacts and selective emitter regions are concurrently formed.

As in the setups in FIGS. 21 and 22, multilayer materials may be coatedon each side of the 3-D TFSC substrate by using multiple sets ofliquid-dip applicators (not shown here) and applying (or flowing) adifferent liquid source material to each liquid-dip applicator on thetop and/or rear set of applicators. This type of processing system mayalso be used for applying metal liquid for fire-through metallization aswell as applying liquid etchant for selective etching of dielectrics(e.g., oxide and/or solid dopant source layer) from the top and/or rearhexagonal prism ridges.

FIG. 24 shows a 3-D view 500 of multiple adjacent prism unit cells froma regular hexagonal prism TFSC of this disclosure, after cellfabrication, including self-aligned base and emitter contactmetallization. The dark region on the top 502 of the unit cell is theself-aligned emitter contact metal; the rear 504 of the unit cell is theself-aligned base contact metal. The prism sidewall surfaces are dopedto form the selective emitter junctions (e.g., shallow n⁺p junctionswith a junction depth of 0.2 to 0.5 micron in boron-doped silicon base).

FIGS. 25A through 31 show various cross-sectional views ofhexagonal-prism unit cells with rear base layers, with detached orintegrated/attached rear mirrors. These FIGURES correspond to the cellfabrication process flow embodiments outlined in FIGS. 15-20. The celldoping polarities may be inverted (e.g., phosphorus-doped base and p⁺nselective emitter). While depicted for c-Si cells, this cell structuremay also be applied to polysilicon, amorphous silicon, and non-Siabsorber TFSCs. The substrates shown have tapered prism sidewalls(narrower emitter and wider base). Alternatively, the substrate may havevertical prism sidewalls.

FIG. 25A shows a Y-Y cross-sectional view 510 of a unit cell within asingle-aperture hexagonal-prism 3-D TFSC substrate with a rear baselayer (released and removed from its template) before cell fabrication.For subsequent n⁺p selective emitter formation, the hexagonal-prismsidewalls are in-situ-doped with boron to form the base region at thetime of 3-D TFSC substrate fabrication. The sidewalls are doped withboron (in one embodiment, at the time of silicon deposition into thetemplate), either uniformly or in a graded profile, more lightly dopedat the prism sidewall surface and more heavily doped towards thesidewall vertical center axis. Similarly, the hexagonal-prism rear baselayer is in-situ-doped at the time of 3-D TFSC substrate fabrication.The base layer is doped with boron, either uniformly or in a gradedprofile, more lightly doped at the rear base layer top surface and moreheavily doped towards the rear base layer rear surface, creating abuilt-in back-surface-field effect in the rear base layer, improving thecell performance. The prism top (emitter side) ridges 512 are used foremitter contact diffusion and metal contact formation and the hexagonaltroughs 514 for base contact diffusion and buried metal contactformation.

FIG. 25B shows a Y-Y cross-sectional view 520 of a unit cell within thehexagonal prism 3-D TFSC of this disclosure (using the hexagonal prism3-D TFSC substrate with a rear base layer as shown in FIG. 25A) afterself-aligned formation of: selective emitter regions 522 (e.g., lessheavily-doped with phosphorus, n⁺ selective emitter on the hexagonalprism sidewall surfaces as shown); heavily-doped emitter contact regions524 with coverage height L_(e) 526 (e.g., more heavily-doped withphosphorus, n⁺⁺ doped emitter contact regions on the hexagonal prism tophexagonal ridges as shown); selective base regions 528 on the rearsurface of the rear base layer (e.g., less heavily-doped with boron, p⁺selective base on the rear base layer rear surface as shown); andheavily-doped (boron-doped p⁺⁺) base contact diffusion regions 530 inthe rear base layer trenches/troughs (e.g., more heavily-doped withboron, p⁺⁺ doped base contact regions). The cured solid dopant sourcelayers for emitter 525 and base regions 532 are shown as dark segmentson the top hexagonal-prism ridges and within the rear base rear filledtrenches (troughs), respectively.

FIG. 26A shows a Y-Y cross-sectional view 540 after the cured n-type andp-type dopant layers have been removed and before the thermal diffusionprocess. FIG. 26B shows a Y-Y cross-sectional view 550 after formationof surface passivation and anti-reflection coating (thermal SiO₂ and/orPVD or PECVD SiN_(x) or AlN_(x) ARC) dielectric layers 552. Note L_(e)554 and cured boron doped glass 556. FIG. 27A shows a Y-Ycross-sectional view 560 after formation of emitter 1732 and base 1734contact metals (silver, aluminum, copper, etc.) by fire-through and/orselective plating. FIG. 27B shows a Y-Y cross-sectional view 570 afterthe addition of a detached highly reflective rear specular or diffusemirror 572 (e.g., silver or aluminum coating on a base interconnectplane on a PCB in the solar module assembly; the mirror may contact therear base contacts as shown).

FIG. 28 shows a Y-Y cross-sectional view 580 after the addition of anintegrated/attached highly reflective thin rear specular or diffusemirror (e.g., a thin layer 572 of silver or aluminum coating depositedby PVD or plating on the rear base layer rear surface as shown; fordiffuse mirror, the dielectric layer on the rear base layer rear surfaceis roughened by a surface roughening process such as a plasma treatmentor ion bombardment before mirror metal deposition). Alternatively, thebase layer may already be textured by a pre-textured template from whichthe TFSC substrate is released.

FIG. 29 shows a Y-Y cross-sectional view 590 of the TFSC in FIG. 28(showing multiple prism unit cells). The TFSC includes an integrated(attached) high-reflectivity rear mirror 572, made of silver oraluminum, which may be deposited (e.g., by PVD or plating or evaporationor another coating technique such as roller or spray coating followed bycuring) on the rear passivation oxide (and ARC) layer(s) formed on therear surface of the rear base layer. Rear mirror 572 is also the baseinterconnect plane, electrically connecting to the self-alignedhexagonal base contacts 592 (e.g., silver and/or aluminum and/or copperor other metals) on the rear base layer. The rear mirror may bedeposited on a smooth or roughened rear base dielectric layer surface(for specular or diffuse mirror, respectively). Again, the base layermay already be textured by a pre-textured template from which the TFSCsubstrate is released.

FIG. 30 shows a Y-Y cross-sectional view 600 of the TFSC in FIGS. 28 and29, with multiple prism unit cells shown. The TFSC includes a detacheddiffuse high-reflectivity rear mirror 602, made of silver or aluminum(mirror coating), placed below the rear surface of the rear base layer.This FIGURE shows the module assembly interconnect plane placed at aspacing of S 604 below the rear surface of the rear base layer, where Smay be in the range of 0 (i.e., interconnect plane in contact with therear base layer rear surface) up to roughly H (where H is the height ofthe hexagonal prism unit cell and may be in the range of 100 to 500microns). In this latter structure, the rear mirror is not electricallyconnected to the base contact metal. Without the integrated mirror, theinterconnect plane with a suitable coating (in one embodiment, silver)may serve as a detached rear mirror.

FIG. 31 shows a schematic Y-Y cross-sectional view 610 of the TFSC inFIG. 27A, with multiple prism unit cells shown. The TFSC includes adetached diffuse high-reflectivity rear mirror 612, made of silver oraluminum (mirror coating), placed below the rear surface of the rearbase layer. This FIGURE shows the mirror placed at a spacing of S belowthe rear surface of the rear base layer, where S may be in the range of0 (i.e., mirror in contact with the rear base layer rear surface) up toroughly H (where H is the height of the hexagonal prism unit cell andmay be in the range of 100 to 500 microns). In this structure, the rearmirror is electrically connected to the base contact metal. Thus, therear mirror shown here also serves as the base interconnect plane.

In the following section, alternative embodiments of process flows forfabricating templates using either lithography and etch techniques orlaser micromachining (or laser drilling) are described. The templatesare then used and reused numerous times to fabricate the 3-D TFSCsubstrates with single-aperture or dual-aperture configurations (eitherwith or without rear base silicon layers) for 3-D TFSC fabrication.

Templates may be fabricated using electronic-grade silicon wafers,solar-grade silicon wafers, or lower-cost metallurgical-grade siliconwafers. Moreover, templates made of silicon can be fabricated eitherusing monocrystalline or multicrystalline silicon wafers. The startingtemplate wafer may either be a standard polished wafer (after saw damageremoval) or even a lower grade wafer immediately after wire sawing(without saw damage removal). The latter may further reduce the cost ofthe templates. The relatively low cost of each template is spread overnumerous 3-D TFSC substrates, resulting in much lower TFSC substrate andfinished module costs compared to the standard state-of-the-art (e.g.,200 microns thick) solar-grade monocrystalline and multicrystallinesilicon wafers and associated modules.

For further explaining how a template is fabricated, FIG. 32 shows anembodiment of a process flow 620. The process begins with step 622,where an unpatterned monocrystalline silicon or multicrystallinesilicon, either square-shaped or round substrate (e.g., 200 mm×200 mmsquare or 200-mm round) is provided. The starting template wafer may bea wafer prepared by wire saw either with or without saw damage removal(the latter may further reduce the cost of template). The startingtemplate wafer may also be made of a lower purity (and lower cost)metallurgical-grade silicon. In one embodiment, the substrate is roughly200 to 800 microns thick. Optionally, step 622 includes performinggettering on a low-cost metallurgical-grade silicon and/or performing asurface texturing etch (e.g., using isotropic acid texturing by amixture of nitric acid and hydrofluoric acid, or using alkalinetexturing in KOH/IPA) to create an optional textured template surface.Step 624 uses photolithography patterning (in one embodiment, using alower cost contact or proximity aligner/patterning) to produce aprism-array mask pattern such as hexagonal-array pattern in photoresist(i.e., interconnected hexagonal openings in the photoresist layer). Theprocess sequence includes the formation of an oxide and/or nitride(optional) layer, photoresist coating (e.g., spin-on or spray coating)and pre-bake, photolithography exposure through a hexagonal-array mask,and photoresist development and post-bake. One embodiment includes ahard mask layer (SiO₂ and/or SiN_(x); for example, a thin thermallygrown oxide layer can be used as an optional hard mask) below thephotoresist (although the process may be performed without the use ofany hard mask layer by placing the photoresist coating directly onsilicon). When using a hard mask layer, the exposed portions of the hardmask layer are etched after photoresist patterning (thus, forminghexagonal openings). Such etching of the exposed hard mask layer may besimply performed using a wet etchant such as hydrofluoric acid for oxidehard mask. Step 626 involves formation of hexagonal prisms usinganisotropic plasma etch; where a high-rate deep reactive ion etch (DRIE)process forms a closely-packed array of deep (e.g., 100 to 400 microns)hexagonal-shaped trenches in silicon. The photoresist and/or oxideand/or nitride hard mask layer(s) are used for pattern transfer from thepatterned photoresist layer to silicon. In one embodiment, the deep RIE(DRIE) process parameters are set to produce near-vertical, slightlytapered hexagonal-prism trench sidewalls. In an alternative embodiment,the deep RIE (DRIE) process parameters are set to produce roughly oressentially vertical hexagonal-prism sidewalls. Note that the slightlytapered sidewalls are preferred over the essentially vertical sidewalls.Step 628 involves template surface preparation and cleaning. Thisprocess includes stripping the patterned photoresist layer from thesubstrate. The template substrate is then cleaned in a wet bench priorto subsequent thermal deposition processing to form the TFSC substrates.Such cleaning may involve DRIE-induced polymer removal (using a suitablewet etchant such as a mixture of sulfuric acid and hydrogen peroxide)followed by an isotropic silicon wet etch (such as in a mixture ofnitric acid and hydrofluoric acid) in order to isotropically remove athin layer (e.g., on the order of 10 to 500 nanometers) of silicon fromthe trench sidewalls and bottoms. This may remove any surface and buriedcontaminants, such as any surface and embedded metallic and/orpolymeric/organic contaminants introduced by the deep RIE (DRIE)process, from the sidewalls and bottoms of the DRIE-produced templatetrenches. Template processing may complete after a deionized (DI) waterrinse and drying. Optionally and if desired, the template wafer may alsogo through a standard pre-diffusion (or pre-thermal processing) wafercleaning process such as a so-called RCA wet clean prior to theabove-mentioned DI water rinsing and drying. Another optional surfacepreparation step (either performed instead of or after the wet isotropicsilicon etch process) includes performing a short thermal oxidation(e.g., to grow 5 to 100 nanometers of sacrificial silicon dioxide),followed by wet hydrofluoric acid (HF) oxide strip (to remove anyresidual contaminants from the patterned template). If no optional oxidegrowth/HF strip is used, an optional dilute HF etch may performed toremove the native oxide layer and to passivate the surface with hydrogen(forming Si—H bonds) in preparation for subsequent 3-D TFSC substratefabrication. After the completion of step 628, the resulting templatemay then be used and reused multiple times to fabricate 3-D (e.g.hexagonal-prism) TFSC substrates.

FIG. 33 shows a top view of a lithography exposure mask design 630 whichmay be used for fabrication of a template, as described in step 624 ofprocess flow 620 above. Dark regions 632 are an opaque coating such asCr on a transparent mask plate. Light regions 634 are areas where theopaque coating (e.g., Cr) has been etched to allow for exposure of aphotoresist layer. In one embodiment, the width of the hexagonal line(L_(M)) 635 on the mask plate is between 1 and 30 microns, and thediagonal distance between hexagonal prism points (d) 636 or thehexagonal-prism aperture diameter is between 50 and 500 microns.

An alternative embodiment of a process flow 640 for patterning of atemplate is outlined in FIG. 34, which uses direct laser micromachininginstead of photolithography and reactive-ion etch. Step 642 (providingan unpatterned substrate) corresponds to step 622 of FIG. 32. Step 644involves the use of programmable precision laser micromachining to formthe desired periodic array of deep trenches. This process may beperformed in a controlled atmospheric ambient based on either physicalablation or a combination of physical ablation and laser-assistedchemical etching. Step 646 (surface preparation and cleaning)corresponds to step 628 of FIG. 32. After the completion of step 646,the resulting template may then be used and reused to fabricate multiple3-D TFSC substrates.

Another alternative embodiment of a process flow 650 for patterning of atemplate is outlined in FIG. 35, which uses photolithography and etch toproduce through-wafer trenches. Step 652 (providing an unpatternedsubstrate) corresponds to step 642 in FIG. 134. Step 654 involvesforming a silicon dioxide (SiO₂) layer and/or a silicon nitride(SiN_(x)) layer on both the frontside and backside of the substrate(this step is optional and may not be used). In one embodiment, the SiO₂layer thickness is between 100 and 1000 nanometers. The SiO₂ layer isformed by steam oxidation or LPCVD and may be followed by a layer ofSiN_(x) formed by LPCVD or PECVD. In one embodiment, the SiN_(x) layerthickness is between 100 and 1000 nanometers. These layers may be formedon both sides of the silicon substrate (as shown in FIG. 34), or only onthe substrate frontside or backside. Alternatively, only one layer(either oxide or nitride) may be used. Step 656 (patterning) correspondsto step 624 in FIG. 32; and step 658 (etch) corresponds to step 626.Step 660 involves formation of backside oxide/nitride openings for 3-DTFSC substrate release etching. Photoresist lithography patterning andplasma etch (or wet etch) are used to form a regular array of openings(e.g., a square grid or a line pattern) in oxide/nitride on thesubstrate backside. These openings may be used during subsequent 3-DTFSC substrate fabrication (for wet etchant access to sacrificial layerfrom backside). Step 662 (surface preparation and cleaning) correspondsto step 628 in FIG. 32 and may be modified such that the surfacepreparation and cleaning process does not remove the dielectric layersfrom the substrate backside. After step 662, the resulting template maythen be used to fabricate 3-D TFSC substrates.

Another alternative embodiment of a process flow 670 for fabrication ofa template is outlined in FIG. 36, which uses photolithography and etch,enabling fabrication of TFSC substrates with a rear base layer andgrooves for formation of self-aligned base contacts. Another alternativeembodiment of a process flow 670 for patterning of a template isoutlined in FIG. 37, which uses photolithography and etch, enablingfabrication of TFSC substrates with a rear base layer and grooves forformation of self-aligned base contacts. FIGS. 41 through 47 show theY-Y cross-sectional views of a silicon substrate during the fabricationprocess flow for making a template based on the process flows of FIG. 36or FIG. 37. It may be useful to refer to FIGS. 41 through 47 whilereviewing the process flow steps of FIGS. 136 and 37.

Referring to FIG. 36, step 672 (providing an unpatterned substrate)corresponds to step 652 in FIG. 35; step 674 (forming oxide and/ornitride layers) corresponds to step 654; step 676 (patterning)corresponds to step 656; and step 678 (etch) corresponds to step 658.Step 680 involves formation of self-aligned shallow trenches which arewider than deep trenches. The self-aligned wider shallow surfacetrenches are formed by a timed selective isotropic dielectric (hardmask) etch to form hard mask undercuts with known lateral dimensionunder photoresist, stripping patterned photoresist, and a timedanisotropic silicon RIE to form shallower/wider tapered trenches nearsurface. Step 682 (formation of backside openings) corresponds to step660 in FIG. 35; and step 684 (surface preparation and cleaning)corresponds to step 662. After step 682, the resulting template may thenbe used and reused to fabricate multiple 3-D TFSC substrates. It shouldbe noted that the self-aligned wider shallow trenches (which are widerthan the deep trenches) may also be formed as part of the same deep RIEprocess which forms the deep trenches (i.e., steps 678 and 680 can bemerged into a single deep RIE process in a DRIE process equipment),thus, eliminating the need for the above-mentioned timed selectiveisotropic dielectric hard mask etch to form hard mask undercuts underphotoresist (this modified approach may also eliminate the need for thefrontside hard mask (i.e., the patterned photoresist layer can be formeddirectly on the substrate) and further simplify the template fabricationprocess). This simplified process can be performed by using a DRIEprocess recipe which first forms the deep hexagonal-prism trenches andsubsequently forms the shallow wider trenches (or shoulders) over thedeep trenches by performing a less anisotropic (or more isotropic)silicon etch process which primarily affects the upper (topmost) portionof the deep hexagonal-prism trenches. Using this modified approach thesidewall profile of the wider shallow trenches may be slightly orheavily tapered (both are acceptable).

Referring to FIG. 37, step 692 (providing an unpatterned substrate)corresponds to step 672 in FIG. 36. Step 694 involves forming a SiO₂layer and/or a SiN_(x) layer on the frontside and optionally on thebackside of the substrate. In one embodiment, SiO₂ layer thickness isbetween 100 and 1000 nanometers. The SiO₂ layer is formed by steamoxidation or LPCVD followed by a layer of SiN_(x) formed by LPCVD orPECVD. In one embodiment, the SiN_(x) layer thickness is between 100 and1000 nanometers. The layers are formed either on front or both sides ofthe silicon substrate. Alternatively, only one layer (oxide or nitride)may be used. Alternatively, a SiO₂ layer only on the frontside and aSiN_(x) layer only on backside may be formed. Step 696 (patterning)corresponds to step 676 of FIG. 36; step 698 (etch) corresponds to step678; and step 700 (formation of shallower wider trenches) corresponds tostep 680. Again and essentially as described for FIG. 14, theself-aligned wider shallow trenches (which are wider than the deeptrenches) may also be formed as part of the same deep RIE process whichforms the deep trenches (i.e., steps 198 and 200 can be merged into asingle deep RIE process in a DRIE process equipment). Step 702 involvesformation of an array of openings on the wafer backside of sufficientdepth to connect to at least some portions of the rears (bottoms) of thedeep trenches. These openings provide access to at least a portion ofeach prism unit cell from the substrate backside. These holes are formedby laser drilling (or may be formed using backside lithography and wetor plasma etch) and may be used for 3-D TFSC substrate release etching(for etchant access to sacrificial layer such as for etching thesacrificial porous silicon layer). Step 704 (surface preparation andcleaning) corresponds to step 684 of FIG. 36. After step 704, theresulting template may then be used and reused to fabricate multiple 3-DTFSC substrates.

FIGS. 36 and 37 result in templates which enable subsequent fabricationof 3-D TFSC substrates with rear base layers (e.g., such as flat rearsilicon base layers) and interconnected shallow grooves or trenches forformation of self-aligned high-conductivity base contact metallization.These 3-D TFSC substrates may be used for subsequent fabrication ofhigh-efficiency TFSCs with self-aligned base and emitter contacts. Thedual-width trenches (or deep trenches with shallower and wider trenchshoulders stacked on their top) in the template enable fabrication ofself-aligned base metallization contacts beside self-aligned emittermetallization contacts.

In order to better understand the following FIGURES, FIG. 38 is providedto show a top view of a hexagonal prism 3-D TFSC substrate. FIG. 38shows the reference imaginary Y-Y and Z-Z cross-sectional axes on ahexagonal-prism 3-D TFSC substrate.

FIG. 39 shows a Y-Y cross-sectional view of a template 780 withthrough-wafer trenches 782 (i.e., trenches formed through the substrateand stopped on backside dielectric). This template 780 may be used tofabricate numerous hexagonal-prism 3-D TFSC substrates, including thosewithout rear base layers (i.e., dual-aperture TFSC substrates).

The template 780 has dimensions of h (horizontal distance betweentrenches) 784, T_(st) (trench top width) 786, H (height of the trench)788, T_(sb) (trench rear width) 790, and 2θ 792 (where θ is the averagesidewall taper angle). Note that because these are through-wafertrenches, H 788 is essentially the same as the silicon thickness of thetemplate substrate. Because the through-wafer trenches 782 produceisolated posts, backside dielectric layer 794 is used and should besufficiently thick and strong to provide sufficient mechanical support.Backside dielectric layer 794 may be a single dielectric layer such asoxide (or nitride) or a stack of two or more dielectric layers such asoxide/nitride. In one embodiment, backside dielectric layer 794 iscomposed of a layer of LPCVD Si₃N₄ on top of a layer of thin thermalSiO₂. The template 780 contains a frontside etch-stop layer (top hardmask layer) 796. In one embodiment, the top hard mask 796 is composed ofa layer of LPCVD Si₃N₄ on top of a layer of thin thermal SiO₂.Alternatively, the top hard mask layer 796 may include a single layerinstead of a 2-layer stack (e.g., Si₃N₄, SiC_(x), etc.). Alternatively,there may be no top hard mask layer (patterned photoresist formeddirectly on silicon).

FIG. 40 shows a Y-Y cross-sectional view of a template 800 with in-wafertrenches 802. This template 800 may also be used to fabricate numeroushexagonal-prism 3-D TFSC substrates, including those without rear baselayers (i.e., dual-aperture TFSC substrates). The trenches are confinedwithin the wafer (within the template substrate) and do not penetratethe entire wafer thickness, leaving remaining wafer thickness R 804;note that for a given template substrate thickness, H 806 is less than H788 in FIG. 39. Thus, the wafer itself provides sufficient mechanicalsupport without a need for mechanical support from backside dielectrics(thus, eliminating the need for backside dielectrics; backsidedielectrics are optional here).

The trenches formed in the templates shown in FIGS. 39 and 40 may havevertical sidewalls or slightly tapered sidewalls (in one embodiment,producing deep trenches with gradually and slightly decreasing trenchwidth moving from the trench top towards the trench bottom). In oneembodiment, sidewall angles are in the range of 0° to 100 (preferably inthe range of 0° to 1°). Trenches with negative or re-entrant sidewallangles (i.e., trenches with increasing trench width moving from thetrench top towards the trench bottom) are not desirable and may causedifficulty with 3-D TFSC substrate release and, therefore, should beavoided.

Both template 780 (FIG. 39) and template 800 (FIG. 40) are made usingone of the template process flows outlined in FIGS. 34-36. Theseflowcharts describe the preferred process steps used for fabricating thetemplates used for subsequent fabrication of numerous 3-D TFSCsubstrates.

FIGS. 41 through 47 show one embodiment of a process flow and evolutionof a template structure for a template version with in-wafer trenches800 and design to enable formation of self-aligned base contacts duringvarious stages of the template process flows outlined in FIGS. 34-36.

FIG. 41 shows a Y-Y cross-sectional view 810 after formation of aphotoresist frontside pattern 812 on dielectric (oxide) hard mask(backside dielectrics 794 are optional and may not be used). FIG. 42shows a Y-Y cross-sectional view 820 after anisotropic plasma oxide etch(or isotropic wet oxide etch) through the photoresist frontside pattern812. FIG. 43 shows a Y-Y cross-sectional view 830 after formation ofdeep hexagonal-prism trenches using deep RIE (DRIE). FIG. 43 furthershows remaining wafer thickness R′ 832 and trench height H′ 834. FIG. 44shows a Y-Y cross-sectional view 840 after timed selective isotropichard mask etch (e.g., oxide etch using HF) to form controlled lateralundercuts 842 under patterned photoresist 812 with width W_(ox). FIG. 45shows a Y-Y cross-sectional view 850 after photoresist strip. Note thatthe top hard mask layer 796 remains and the photoresist layer has beenremoved. FIG. 46 shows a Y-Y cross-sectional view 860 after anisotropicsilicon etch to form wider shallow trenches with controlled height (L)862 on the top of the narrower and deeper trenches 802. FIG. 47 shows aY-Y cross-sectional view of a completed template 870 after isotropicoxide etch to strip the top hard mask layer 796 as shown in FIG. 46.While shown here, the backside dielectric layers may also be removed (ormay not be used at all). This template 870 may also be used to fabricatenumerous hexagonal prism 3-D TFSC substrates. As described before, thecombination of deep trenches and wider shallow trenches (top shoulders)may be formed using a single DRIE process sequence (anisotropic deeptrench RIE followed by a less anisotropic silicon etch to form the topshoulders), thus, eliminating the need for the top dielectric hard masklayer 796 and the associated process steps reflected in FIGS. 46 and 47.

The following FIGURES (FIGS. 48 to 51) illustrate several alternativeembodiments of completed templates.

FIG. 48 shows a Y-Y cross-sectional view of a template 880 with in-wafertrenches 802 without a dielectric top mask layer or a dielectric rearmask layer. FIG. 49 shows a Y-Y cross-sectional view of a template 890with in-wafer trenches 802 without a dielectric top mask layer or adielectric rear mask layer, compared to the embodiment shown in FIG. 48.This view also shows template backside holes 892 used to allow for 3-DTFSC substrate release etching. These backside holes 892 may befabricated using either lithography and etch, or laser micromachining ordrilling. FIG. 50 shows a Y-Y cross-sectional view of a template 900with through-wafer trenches 782 without a top hard mask layer 796 asshown in FIG. 39. FIG. 51 shows a Y-Y cross-sectional view of a template910 with through-wafer trenches 782 without a top hard mask layer 796,compared to FIG. 50. Note further that the through-wafer trenches 782 inFIG. 51 have wider trenches (top shoulders) with controlled height (L)862 on the top of the narrower and deeper hexagonal trenches, like thetrenches in FIG. 47. However, note that FIG. 51 shows through-wafertrenches 782, whereas FIG. 47 shows within-wafer trenches 802.

For templates with through-wafer trenches, mechanical support may beprovided by either using a backside dielectric stack of sufficientstrength (such as oxide, nitride, polysilicon, or a combination thereofas described before), or using a backside-bonded silicon wafer. FIG. 52shows a view of a template 920 with through-wafer trenches and withoutany frontside dielectrics, suitable for fabrication of hexagonal-prismsingle-aperture 3-D TFSC substrates with rear base layers. This template920 includes a mechanical support rear silicon wafer 922 bonded at abonded interface 924 (e.g., via a dielectric such as oxide or adielectric stack 926 such as oxide/nitride between the wafers). Themechanical support rear silicon wafer 922 provides wet etchant access tothe template trenches through holes 928, which may be created either bylaser drilling or reactive ion etching. This template 920 enablesfabrication of 3-D TFSC substrates with capability for formation ofself-aligned base and emitter contacts during subsequent hexagonal prism3-D TFSC substrate fabrication. In an alternative embodiment, mechanicalsupport rear silicon wafer 922 may instead be formed by a layer ofpolysilicon deposited by LPCVD over the backside dielectric (ordielectric stack) 926, thus, eliminating the need for wafer bonding.

FIGS. 53 and 54 show views 930 and 940, respectively, of two examples ofmask designs (out of many possible designs), the first one asquare-array mask and the second one a line-array mask, which may beused to pattern the template backside to produce backside openings for3-D TFSC substrate release etching. This patterning is performed onlyonce on each template.

FIG. 53 shows a square-array mask, where each square-array unit cell 932has a square-array unit cell width 934 and a square array unit cellspacing 936. In one embodiment, both of these are approximately 1 to 5microns (may be smaller or larger as well). FIG. 54 shows a line-arraymask, where the pattern shown is repeated over the entire mask as aperiodic array. In one embodiment, the line widths and spaces are all 1to 10 microns (may be smaller or larger as well). The pattern has apattern width 942, which in one embodiment is approximately 50 to 500microns. Other mask patterns (e.g., lines, circles, etc.) enablingetchant access to remove the sacrificial layer may be used instead ofsquare array or orthogonal line array. Alternatively, it is possible touse laser drilling or laser micromachining instead of lithography/etchto create the backside holes/openings for etchant access.

An alternative to the backside patterning outlined in FIGS. 53 and 54uses a frontside mask to enable release of single-aperturehexagonal-prism 3-D TFSC substrates with flat base layers by providingetchant access pathways from the template frontside.

FIG. 55 shows an alternative frontside hexagonal-prism mask design 950with center holes 952, shown as white circles on the mask plate. In oneembodiment, center holes 952 are roughly 1 to 5 microns in diameter.Note that the hexagonal-prism array design is the same as in FIG. 33.Dark regions 632 are opaque coating (e.g., Cr) on the mask plate. Lightregions 634 and 952 are areas to be etched. In one embodiment, the widthof the line mask (L_(M)) 635 is between 1 and 30 microns, and thediagonal distance between hexagonal-prism points (d) 636 is between 50and 500 microns.

FIG. 56 shows the template frontside mask design 950 shown in FIG. 55,also shown with dotted squares 954 indicating a superimposed image ofone embodiment of the backside mask design (in order to see the relativealignment of the frontside mask and backside mask from the frontsidemask perspective).

FIG. 57 shows a top view of a template backside mask design 960, withthe superimposed image of the hexagonal array of the mask design 950from FIGS. 55 and 56 shown as gray hexagonal-array pattern in order tosee the relative alignment of the frontside mask and backside mask fromthe backside mask perspective).

FIGS. 58 through 66 show an alternative template version during variousstages of the template process flows outlined in FIGS. 36 and 37.

FIG. 58 shows a Y-Y cross-sectional view of an n-type (e.g.,phosphorus-doped) [100] silicon substrate 970 after formation of a tophard mask layer 796 and a backside hard mask layer 794 using thermaloxidation. Note that before oxidation, an optional surface texturing wetetch (such as using an acid texturing etch or an alkaline texturingetch) may be performed using a suitable etchant such as KOH in order totexture the silicon surface. FIG. 59 shows the substrate 970 in FIG. 58after backside lithography to form a patterned photoresist layer 974comprising an array of square-shaped openings 972 and after wet oranisotropic plasma etching of the backside hard mask layer 794 in theexposed areas. Note that in order to use anisotropic wet etch to formthe backside channels, the backside mask square pattern for thesubstrate 970 backside is properly aligned to produce [111] sidewalls,[110] directed edges, and [211] directed ribs. FIG. 60 shows thesubstrate 970 in FIG. 59 after anisotropic etching of template frombackside using an anisotropic wet etchant (e.g., KOH or TMAH) to form anarray of pyramids 976 with square bases and after stripping photoresistlayer 974 from template backside. Note the angle 978 of the pyramids976. In one embodiment, this angle is 35.26°. The backside lithographymask square pattern is properly aligned to produce [111] plane sidewalls980, [110] directed edges, and [211] directed ribs. FIG. 61 shows thesubstrate 970 in FIG. 60 after frontside patterning and anisotropicoxide plasma etch (or isotropic oxide wet etch) through patterned resist812 in preparation for formation of honeycomb-prism trenches andconcurrently forming frontside-etched small-diameter release trenches982, and removing backside oxide layer 794. In one embodiment, thediameter (DR) of the release access trenches 982 is between 1 and 5microns. FIG. 62 shows the substrate 970 in FIG. 61 after frontside deepsilicon RIE. Note that frontside-etched small-diameter trenches 982connect to the backside release channels 976 through shallowercone-shaped trenches 984 (in one embodiment, at the centers of thehexagonal-prism posts). FIG. 63 shows the substrate 970 in FIG. 62 aftertimed selective isotropic hard mask (SiO₂) etch to form controlledlateral undercuts 842 under patterned photoresist. FIG. 64 shows thesubstrate 970 in FIG. 63 after photoresist 812 strip, with oxide hardmask 796 remaining. FIG. 65 shows the substrate 970 in FIG. 64 afteranisotropic silicon reactive-ion etch to form wider trenches withcontrolled height (L) 862 on top of the narrower and deeperhexagonal-prism within-wafer trenches 802. FIG. 66 shows the substrate970 in FIG. 65 after isotropic oxide etch to strip top oxide 796. Afterthis step an optional timed silicon wet etch may be performed in HNA orTMAH to remove about 5 to 500 nanometers of silicon to remove anyDRIE-induced trench sidewall damage and/or polymeric/metalliccontamination. At this point, the substrate 970 may serve as a reusabletemplate for formation of 3-D TFSC substrates. Again as describedbefore, the combination of deep trenches and wider shallow trenches (topshoulders) may be formed using a single DRIE process sequence(anisotropic deep trench RIE followed by a less anisotropic silicon etchto form the top shoulders), thus, eliminating the need for the topdielectric hard mask layer 796 and the associated process stepsreflected in FIGS. 64 and 65. This alternative process flow alsoeliminates the need for the oxide hard mask (thus, photoresist can beapplied directly on silicon for frontside and backside patterningsteps).

FIGS. 67 through 75 show a template version during various stages of thetemplate fabrication process flow outlined in FIGS. 36 and 37. FIGS. 67through 75 are substantially similar to FIGS. 58 through 66, except theinitial silicon substrate is an n-type [110] substrate 990, whichresults in backside release channels 992 in the shape of rectangulartrenches with vertical sidewalls, rather than pyramids. The resultingsubstrate 990 shown in FIG. 75 may serve as a reusable template forformation of 3-D TFSC substrates. Again as described before, thecombination of deep trenches and wider shallow trenches (top shoulders)may be formed using a single DRIE process sequence (anisotropic deeptrench RIE followed by a less anisotropic silicon etch to form the topshoulders), thus, eliminating the need for the top dielectric hard masklayer 796 and the associated process steps reflected in FIGS. 72 and 73.This alternative process flow also eliminates the need for the oxidehard mask (thus, photoresist can be applied directly on silicon forfrontside and backside patterning steps).

Another approach to implement the template release channels is to placethem on the template substrate backside such that they connect to thebottoms of the hexagonal-prism deep trenches (instead of tops of theposts or pillars as shown before). FIGS. 76 and 79 through 86 show atemplate version (with the release channels connected to the bottoms ofthe deep trenches) during various stages of the template process flowsoutlined in FIGS. 36 and 37. This embodiment uses a backside lithographymask design as shown in FIG. 77 (other types of backside mask patternsfor backside release channels are also possible). FIG. 78 shows thebackside lithography mask shown in FIG. 77, with the frontsidehexagonal-prism array mask pattern shown as a superimposed gray patternfor reference (to show the relative alignment of the frontside andbackside masks patterns).

FIG. 76 is substantially similar to FIG. 58 above, showing an initialn-type (e.g., phosphorus doped) [100] substrate 970. FIG. 79 issubstantially similar to FIG. 59 above, except the mask design alignsbackside release channels 994 with the bottoms of deep prism trenches802 to be formed. FIG. 80 shows the substrate 970 shown in FIG. 79 afteranisotropic wet etching (e.g., using anisotropic alkaline etching suchas KOH-based etching) of the template backside to form an array ofpyramids with square bases (note that the anisotropic etching may alsobe performed using anisotropic reactive ion etching and the backsideopenings may be circular or other shapes instead of square-shaped). FIG.81 shows the substrate 970 in FIG. 80 after frontside patterning andafter wet oxide etch through patterned resist in preparation forformation of deep trenches. This also removes the backside oxide layer794. FIG. 82 shows the substrate 970 in FIG. 81 after formation ofhexagonal-prism trenches 802 using deep RIE (DRIE). Note that thebottoms of prism trenches 802 essentially align with the backsiderelease channel holes 994. FIG. 83 shows the substrate 970 in FIG. 82after timed selective isotropic hard mask (in one embodiment SiO₂) wetetch to form controlled lateral undercuts 842 under patternedphotoresist. FIG. 84 shows the substrate 970 in FIG. 83 after topphotoresist 812 strip using a photoresist stripper. FIG. 85 shows thesubstrate 970 in FIG. 84 after anisotropic silicon etch (using the oxidelayer as a hard mask) to form wider trenches (top shoulders) withcontrolled height (L) 862 on top of the narrower and deeperhexagonal-prism within-wafer trenches 802. FIG. 86 shows the substrate970 in FIG. 85 after isotropic oxide etch to strip top oxide 796. Afterthis step an optional timed isotropic silicon wet etch may be performedin HNA or TMAH (or another suitable isotropic silicon wet etchant) toetch approximately 5 to 500 nanometers of silicon to remove anyDRIE-induced trench sidewall contaminants (such as metallic and/orpolymeric contaminants) and surface damage. At this point, the substrate970 may serve as a template for formation of 3-D TFSC substrates. Againas described before, the combination of deep trenches and wider shallowtrenches (top shoulders) may be formed using a single DRIE processsequence (anisotropic deep trench RIE followed by a less anisotropic ormore isotropic silicon plasma etch to form the top shoulders), thus,eliminating the need for the top dielectric hard mask layer 796 and theassociated process steps reflected in FIGS. 83 and 84. This alternativeprocess flow also eliminates the need for the oxide hard mask (thus,photoresist can be applied directly on silicon for frontside andbackside patterning steps).

Various embodiments of the templates shown earlier may be used toproduce one hexagonal-prism (or other prism geometries) 3-D TFSCsubstrate per process pass. It is also possible to fabricate templateswhich are capable of producing two hexagonal-prism 3-D TFSC substratesconcurrently per process pass (thus, doubling the 3-D TFSC substratefabrication throughput). FIGS. 87 and 88 show cross-sectional views oftwo such templates capable of doubling the hexagonal-prism 3-D TFSCsubstrate production throughput.

FIG. 87 shows a Y-Y cross-sectional view of a stacked template structure1000 for fabricating two hexagonal prism 3-D TFSC substrates per processpass. FIG. 87 shows a template structure 1000 with in-wafer trenches802. Note the similarity to the template 800 in FIG. 40. Templatestructure 1000 is made of two similar templates, a top template 1002 anda rear template 1004, which are first fabricated based on one of theembodiments outlined before and then bonded together backside tobackside (e.g., using direct thermal bonding of the wafer backsides orthermal bonding of dielectric layers formed on the wafer backsides) at abackside interface 1006. Note that the dielectric hard masks on thetemplate frontsides may not be present (they are optional for subsequentuse of the templates for TFSC substrate fabrication). FIG. 88 shows Y-Ycross-sectional view of an alternative stacked template structure 1010for concurrently fabricating two hexagonal-prism 3-D TFSC substrates perprocess pass. FIG. 88 shows a template structure 1010 with through-wafertrenches 782. Note the similarity to the template 780 in FIG. 39.Template structure 1010 is made of two similar templates, a top template1012 and a rear template 1014, which are first fabricated based on oneof the embodiments outlined before and then bonded together backside tobackside (e.g., either through direct bonding of the substrate backsidesor using thermal bonding of dielectric layers formed on the waferbacksides) at a backside interface 1006. Note that the dielectric hardmasks on the template frontsides may not be present (they are optionalfor subsequent use of the templates for TFSC substrate fabrication).

While FIGS. 87 and 88 show representative stacked template structuressuitable for higher throughput fabrication of hexagonal-prismdual-aperture 3-D TFSC substrates without rear base layers, it is alsopossible to make stacked template structures for fabrication ofhexagonal prism 3-D TFSC substrates with rear base layers. This may bedone by first fabricating the suitable individual templates based on oneof the process flow embodiments shown in FIGS. 36 and 37, correspondingto the template structure shown in FIG. 47 (this one shown with in-wafertrenches; it is also possible to fabricate templates with through-wafertrenches such as the structures shown in FIG. 51 or FIG. 52). Assumingwe use a pair of templates with the structure shown in FIG. 47 (or atemplate structure with wider and shallow trenches or shoulders stackedon top of the deep trenches), these templates are then processed tocreate a series of large lateral/radial microchannels in conjunctionwith an array of holes/openings which communicate with the rears oftrenches. The two templates are then bonded togetherbackside-to-backside (e.g., by thermal bonding of the backside surfacestogether). The radial/lateral microchannels sandwiched between thebonded wafers extend all the way to the periphery of the stacked/bondedtemplates and provide easy access for the wet etchant to reach thesacrificial layer (e.g., porous silicon formed by anodic etching ofmonocrystalline or microcrystalline silicon layer) in each template inorder to selectively remove the sacrificial layer in each template andto release the embedded hexagonal-prism 3-D TFSC substrates from the topand rear templates in the stack (thus, concurrently forming twohexagonal-prism 3-D TFSC substrates per process pass). The microchannelson the template backsides may be formed before template bonding by laserablation or a combination of lithography and etch. The microchannels aresufficiently large to allow for easy movement of wet etchant and etchbyproducts between the inner portions of the wafers in the bonded stackand the peripheral openings of the microchannels in the middle of thebonded stack.

The templates described above may be used to fabricate 3-D TFSCsubstrates for use in 3-D TFSCs.

FIGS. 89 and 90 show two different process flow embodiments forfabricating hexagonal-prism dual-aperture 3-D TFSC substrates with rearbase layers (using a suitable template such as the one shown in FIG.47). FIG. 89 depicts an embodiment of a process flow 1100 using layerrelease processing. This flow is based on the use of Ge_(x)Si_(1-x)sacrificial layer deposition and blanket or selective in-situ-dopedepitaxial silicon deposition. The resulting hexagonal-prism unit cellshave open apertures on prism top and are terminated at the rear with arear base layer (in one embodiment, a relatively flat thin siliconlayer). Again, the process flow of this embodiment may be easilyadjusted in order to use polysilicon, amorphous silicon, or anon-silicon crystalline or polycrystalline/amorphous silicon material.In step 1102, a patterned honeycomb-prism template is provided. Thistemplate has already been processed to form an embedded array oftrenches along with shallower/wider trenches (or trench shoulders)stacked on top of narrower/deeper trenches (see FIG. 47). There is nodielectric layer on the template frontside, and there is a patternedoxide and/or nitride dielectric layer (or stack) with openings left onthe template backside. In step 1104, a multi-layer blanket epitaxy isperformed in an epitaxial reactor, including the following in-situprocess steps. First, H₂ bake or GeH₄/H₂ bake is used for in-situsurface cleaning. Next, a thin Ge_(x)Si_(1-x) epitaxial layer isdeposited (in one embodiment, on the top only). In one embodiment, thislayer is between 10 and 1000 nanometers. Next, a doped silicon epitaxiallayer is deposited on the top only. In one embodiment, this layer isp-type, boron-doped and between 1 and 30 microns thick. The in-situdoping (boron doping) profile may be flat or graded. In case of grading,boron doping concentration is gradually increased during the depositionof the silicon epitaxial layer, with a lower concentration at thebeginning and a higher concentration towards the end of the epitaxialgrowth process. This graded base doping may provide a field-assisteddrift component for efficient collection of photo-generated carriers,substantially reducing the impact of recombination losses. It alsoreduces base sheet resistance and ohmic losses. The silicon epitaxiallayer thickness is set such that the deep trenches are fully filled withsilicon while the shallow (wider) trenches (top trench shoulders)receive epitaxy on their sidewalls and their central regions are leftwith self-aligned shallow hexagonal troughs. In step 1106, the 3-D TFSCsubstrate is released. A highly selective isotropic wet or dry etch ofGe_(x)Si_(1-x) is performed, with very high selectivity with respect tosilicon. In one embodiment, a mixture of hydrofluoric acid, nitric acidand acetic acid (HNA) is used to selectively etch the Ge_(x)Si_(1-x)layer. Alternatively, a mixture of ammonia, peroxide, and water(NH₄OH+H₂O₂+H₂O) may be used. The wet etchant selectively removes thesacrificial Ge_(x)Si_(1-x) layer by reaching the sacrificial layerthrough the template backside dielectric openings. This process releasesthe hexagonal prism 3-D TFSC substrate, which may then be used forsubsequent 3-D TFSC fabrication. Note that the template backsideopenings may be formed directly in silicon backside without a need forthe backside dielectric.

FIG. 90 depicts an embodiment of a process flow 1110 for fabrication ofself-supporting hexagonal-prism single-aperture 3-D thin-filmpolysilicon or amorphous silicon TFSC substrates with rear base layersmade of polysilicon or amorphous silicon using layer release processing,without the use of epitaxial silicon processing. The amorphous siliconor polysilicon layer may be optionally crystallized using lasercrystallization as part of the flow. This process flow uses a dielectricsacrificial layer such as SiO₂ (deposited using LPCVD or thermallygrown) in conjunction with conformal amorphous silicon or polysilicondeposition for the silicon absorber layer. Step 1112 (providing asubstrate) corresponds to step 1102 in FIG. 89. Step 1114 involvesdepositing a conformal sacrificial layer (or a layer stack). First, athin layer of a sacrificial material is deposited by conformal layerformation (LPCVD or thermal oxidation). In one embodiment, thesacrificial material is SiO₂, with a thickness of between 50 and 2000nanometers. This sacrificial oxide layer conformally covers thehexagonal-prism trench walls and the template frontside. If subsequentlaser crystallization is used, step 1114 also includes depositing a thinnitride layer by LPCVD. In one embodiment, this nitride layer is Si₃N₄,with a thickness between 100 and 1000 nanometers. The sacrificial layermay be made of porous silicon instead of oxide and/or nitride. Step 1116involves deposition of a blanket silicon layer using conformaldeposition. In one embodiment, this blanket silicon layer may beamorphous silicon or polysilicon, p-type in-situ doped with boron,having a thickness between 1 and 30 microns. Note that the siliconthickness is set such that the deep trenches are fully filled withsilicon while the shallow (wider) near-surface trenches receive siliconon sidewalls, and their central regions are left with self-alignedrelatively shallow hexagonal troughs or trenches. Step 1118 involvesdepositing an optional thin silicon nitride dielectric layer on top byLPCVD or PECVD to serve as a protective cap for silicon layer. In oneembodiment, this layer is between 100 and 1000 nanometers. Step 1120involves 3-D TFSC substrate release. In one embodiment and when using asilicon dioxide sacrificial layer, hydrofluoric acid (HF) is used toetch the oxide sacrificial layer. In another embodiment and when using aporous silicon sacrificial layer, a mixture of ammonia, peroxide, andwater (NH₄OH+H₂O₂+H₂O) or a mixture of hydrogen peroxide andhydrofluoric acid (H₂O₂+HF) or a suitable composition oftri-methyl-ammonium-hydroxide (TMAH) may be used. The etch compositionand temperature may be adjusted to achieve maximum etch selectivity forporous silicon with respect to silicon. This process releases thehexagonal-prism 3-D TFSC substrate. Note that the wet etchantselectively removes the sacrificial Ge_(x)Si_(1-x) layer (or poroussilicon sacrificial layer) by reaching the sacrificial layer through thetemplate backside dielectric openings (note that backside openings maybe formed directly in the template substrate backside without using anydielectric on the template backside). This process releases thehexagonal-prism 3-D TFSC substrate from the template. An optional step1122 involves laser crystallization of the released 3-D thin-filmamorphous silicon or polysilicon substrate to form a large-grainpolysilicon microstructure. The silicon nitride layer surroundingsilicon serves as protective cap. The nitride layer is then selectivelystripped. The hexagonal-prism 3-D TFSC substrate may then be used forsubsequent 3-D TFSC fabrication.

FIGS. 91 through 95 illustrate Y-Y cross-sectional views of a template870 (see FIG. 47) with in-wafer hexagonal-prism trenches 802 and nodielectrics on the template frontside and an optional backside layer 794(the template may be fabricated without any frontside and backsidedielectric layers), as it goes through the key process steps tofabricate a hexagonal-prism single-aperture 3-D TFSC substrate with arear base layer. Again, the flow used for this fabrication process flowis based on one of the embodiments outlined earlier.

FIG. 91 shows a view 1130 after deposition of the thin (e.g., 200 to2000 nanometers thick) sacrificial layer 1138 (epitaxial Ge_(x)Si_(1-x)or porous silicon or another suitable material) and the in-situ-doped(boron-doped for p-type base) epitaxial silicon layer 1140. Theepitaxial silicon deposition process fills the trenches (void-freetrench fill) while leaving relatively shallow troughs (trenches) nearthe top. This may be done by stopping the epitaxial deposition processafter the deeper/narrower trenches are fully filled with epitaxialsilicon and before filling of the wider/shallower trenches on thetemplate frontside (thus, forming the shallower troughs with height (L)1132 and width (W_(m)) 1134 in conjunction with the top epitaxialsilicon layer of thickness (W_(f)) 1136. FIG. 92 shows a view 1150 ofthe template in FIG. 91 after highly selective etching of thesacrificial layer 1138, thus allowing for release and removal of the 3-DTFSC substrate 1140 from the template. FIGS. 93 and 94 illustrate Y-Ycross-sectional views 1160 and 1180 of the released substrate 1140 fromFIG. 92. The released substrate 1140 has a base side 1162, an emitterside 1164. The substrate 1140 has dimensions of T_(st) 786 (siliconsidewall thickness near the base side of the hexagonal-prism verticalsidewalls), T_(sb) 790 (silicon sidewall thickness near the emitter sideof the hexagonal-prism vertical sidewalls), hexagonal-prism height 1170,and tapered hexagonal-prism TFSC substrate sidewalls 1172. Referring tothe view 1160 in FIG. 93, the base side 1162 is shown on the top and theemitter side 1164 is shown on the bottom (TFSC substrate as releasedfrom the template). In the view 1180 in FIG. 94, the base side 1162 isshown on the bottom and the emitter side 1164 is shown on the top. FIG.95 shows a Y-Y cross-sectional view 1190 of the template shown in FIG.92 after releasing and separating/removing the embedded hexagonal-prismsingle-aperture 3-D TFSC substrate with a rear base layer (see template870 in FIG. 47). The template 870 is ready for multiple reuse cycles.

FIGS. 96 through 98 illustrate Y-Y cross-sectional views of the template970 from FIG. 66 with square-based pyramid (shown as triangular cavitycross section) backside release channels 976, allowing for releaseetchant access from template backside and subsequent release of the 3-DTFSC substrate. FIG. 96 shows a view 1200 after formation of a suitablesacrificial layer 1202 (made of porous silicon, silicon germanium, oranother suitable material). Note that the through-wafer small-diameter(e.g., 500 to 5000 nanometers) holes 984 are pinched off by porous(microporous or mesoporous) silicon. Porous silicon sacrificial layermay be formed by epitaxial deposition of a thin conformal layer ofp-type silicon and its subsequent conversion to porous silicon (oralternatively by direct conversion of a thin surface layer of thetemplate to sacrificial porous silicon). FIG. 97 shows a view 1210 afterepitaxial deposition of in-situ-doped (e.g., boron-doped for p-typebase) silicon 1140. This step may fill the deep trenches and form theshallow troughs/trenches stacked over the epitaxy-filled deep trenches.FIG. 98 shows a view 1220 after selective wet chemical etching ofsacrificial porous silicon layer 1202 (e.g., in HF/H₂O₂ or TMAH oranother suitable selective etchant for porous silicon) to release andremove the 3-D TFSC substrate 1140 from the template 970.

FIGS. 99 through 101 illustrate Y-Y cross-sectional views of thetemplate 990 from FIG. 75 with square-based (rectangular-shaped)backside release channels 992, allowing for etchant access from thetemplate backside and subsequent release of the 3-D TFSC substrate. FIG.99 shows a view 1230 after formation of a thin sacrificial layer 1202 ofporous silicon. Note that the through-wafer small-diameter holes 984 maybe pinched off by porous (microporous or mesoporous) silicon. FIG. 100shows a view 1240 after epitaxial deposition of in-situ-doped silicon1140. This step may fill the deep trenches and form the shallowtroughs/trenches stacked over the epitaxy-filled deep trenches. FIG. 101shows a view 1250 after selective wet chemical etching of sacrificialporous silicon layer 1202 (e.g., in HF/H₂O₂ or TMAH or another suitableselective etchant) to release the 3-D TFSC substrate 1140 from thetemplate 970.

FIGS. 102 through 104 illustrate Y-Y cross-sectional views of thetemplate 970 from FIG. 86 with backside release channels 994 alignedwith the bottoms of trenches, allowing for backside etchant access andsubsequent release of the 3-D TFSC substrate. FIG. 102 shows a view 1260after formation of a thin (and relatively conformal) sacrificial layer1202 of porous silicon. FIG. 103 shows a view 1270 after epitaxialdeposition of in-situ-doped silicon 1140. This step may fill the deeptrenches and form the shallow troughs/trenches stacked over theepitaxy-filled deep trenches. FIG. 104 shows a view 1280 after selectivewet chemical etching of sacrificial porous silicon layer 1202 (e.g., inHF/H₂O₂ or TMAH or another suitable selective wet etchant) to releaseand remove the 3-D TFSC substrate 1140 from the template 970.

While one embodiment of the 3-D TFSC substrate unit cell structure ofthis disclosure is a regular hexagonal-prism unit cell (with equilateralhexagonal cross sections or ridges), this disclosure also covers a widerange of other 3-D prism unit cell geometrical designs with variouspolygon prism unit cell aperture designs. The prism array may be auniform array of a single polygon prism unit cell or a hybrid (two ormore) of multiple polygon-prism unit cell designs.

FIGS. 105A through 111C show examples of several 3-D polygon-prism TFSCsubstrates with various unit cell prism geometrical designs andarrangements. FIG. 105A shows a top view 1290 of a prism design withhexagonal unit cell angles not equal to one another or 120°. FIG. 105Bshows a top view 1292 of a prism design with equilateral triangularprism unit cells. FIG. 106A shows a top view 1294 of a prism design withnon-equilateral triangular prism unit cells. FIG. 106B shows a top view1296 of a prism design with alternating equilateral triangular prismunit cells. FIG. 107A shows a top view 1298 of a prism design withoffset parallelogram prism unit cells. FIG. 107B shows a top view 1300of a prism design with parallelogram prism unit cells. FIG. 108A shows atop view 1302 of a prism design with aligned square prism unit cells.FIG. 108B shows a top view 1304 of a prism design with shifted squareprism unit cells. FIG. 109A shows a top view 1306 of a prism design withaligned rectangular prism unit cells. FIG. 109B shows a top view 1308 ofa prism design with shifted rectangular prism unit cells. FIG. 110Ashows a top view 1310 of a prism design with trapezoidal prism unitcells. FIG. 110B shows a top view 1312 of a prism design withalternating trapezoidal prism unit cells. FIG. 111A shows a top view1314 of a prism design with hybrid pentagon-parallelogram prism unitcells. FIG. 111B shows a top view 1316 of a prism design with hybridhexagon-triangle prism unit cells. FIG. 111C shows a top view 1318 of aprism design with hybrid octagon-square prism unit cells.

In addition to these alternative TFSC designs, many other polygon-prismas well as other non-polygon prism unit cell designs (e.g.,cylindrical-prism, elliptical-prism, etc.) are covered by thisdisclosure. In general, the 3-D TFSC substrates of this disclosure coverany arrays of one or more prism unit cells arranged to make alightweight, enlarged-surface-area TFSC substrate for solar cellfabrication. Typically, there are millions (or as few as thousands) ofthese prism unit cells forming a large-area (e.g., 210 mm×210 mm) 3-DTFSC substrate. In one embodiment, the 3-D TFSC substrate film thicknessis in the range of 1 to 30 microns, and preferably in the lower-endrange of 2 to 10 microns. This is substantially less (by a factor ofroughly 20× to 100×) than the current state-of-the-art silicon solarcell wafer thickness (roughly 200 microns).

FIGS. 112 through 117 show six different process flow embodiments ofthis disclosure for fabricating dual-aperture hexagonal-prism 3-D TFSCswithout rear base layers. While these process flow embodiments areoutlined for fabricating silicon-based TFSCs, the overall concepts andmethodologies may be extended and applied to other homojunction andheterojunction semiconductor materials (such as multicrystallinesilicon, polycrystalline silicon, CIGS, etc.). While the process flowsshown are for fabrication of 3-D c-Si TFSCs, the embodiments may beeasily adjusted and modified to fabricate silicon-based TFSCs usingpolysilicon, amorphous silicon, and/or multicrystalline silicon films.

FIG. 112 describes a first process flow 1400 for fabricatingdual-aperture hexagonal-prism 3-D TFSCs without rear base layers. Thisflowchart describes the process flow for fabrication of hexagonal-prism3-D TFSCs using self-aligned fire-through metallization with an optionalforming-gas anneal (FGA) process being performed after an optionalselective silver (silver) or selective copper (copper) plating process.This process flow uses roller coating (or spray coating, inkjet spraycoating, or liquid-dip coating) and curing of liquids or pastes ofdopant and metal materials to form the selectively doped emitter regionsas well as emitter and base contact metallization regions. In thisembodiment, while the heavily n⁺⁺ (phosphorus) doped emitter contactregions (for subsequent emitter contact metallization) are formed byusing a cured solid phosphorus dopant source layer formed over thehexagonal-prism top ridges (after thermal anneal), the heavily p⁺⁺ dopedbase contact regions (for subsequent base contact metallization) areformed by aluminum doping of silicon during the fire-throughmetallization process (on the rear hexagonal ridges coated with curedaluminum liquid/paste layer).

Referring to FIG. 112, step 1402 starts with a dual-aperture 3-D TFSCsubstrate (e.g., with in-situ p-type base doping formed during TFSCsubstrate fabrication), with open top and rear apertures (i.e., no rearflat base silicon layer). In step 1404, the top and rear portions of the3-D substrate are selectively coated with n-type dopant (e.g.,phosphorus-containing liquid or paste) and an undoped capping dielectricsealant (e.g., oxide), respectively, from liquid sources. In oneembodiment, these coatings are between 2 and 10 microns in height oneach side of the 3-D TFSC substrate and the n-type dopant is phosphorus.The rear (base side hexagonal ridges) portion of the substrate isselectively coated with undoped capping dielectric sealant such as anoxide. These coatings are applied using liquid or paste sources. Variouscoating embodiments include self-aligned 2-sided roller coating usingpaste/liquid sources, liquid-dip coating by controlled dipping in acontrolled liquid source depth, ink-jet coating, spray coating, oranother suitable coating method. The dopant source and oxide layers arethen dried and cured at 150° C. to 400° C. using flash IR lamp or UVradiation. Step 1406 involves formation of self-aligned selectiveemitter junctions and heavily doped emitter contacts. The top heavilydoped n⁺⁺p emitter contact and honeycomb prism sidewall n⁺p selectiveemitter junctions are concurrently formed by a thermal anneal process(in one embodiment, at 800° C. to 950° C.). Drying/curing and emitteranneal may both be performed sequentially in a belt furnace. The 3-DTFSC substrates, in one embodiment arranged with pairs or stacks of 3-Dsubstrates in face-to-face contact, may be annealed in a heated beltfurnace in order to facilitate gas-phase doping formation of n⁺selective emitter junctions. The rear cap dielectric (e.g., oxide)coating prevents phosphorus doping of the base contact regions. Step1408 involves surface passivation and anti-reflection coating (ARC).First, the top dopant source layer, rear undoped oxide layer, and nativeoxide are stripped using hydrofluoric acid or another suitable etchant(e.g., dilute HF). Next, a thin oxide layer is grown, in one embodimentby steam oxidation. In one embodiment, this layer is between 3 and 300nanometers, performed at 800° C. to 950° C. Next, a passivation and ARClayer is deposited by PECVD or PVD, with coating formed on prism top(emitter side) and selective emitter sidewalls (coating on the base sideis optional). In one embodiment, this layer is between 3 and 150nanometers (preferably between 50 and 100 nanometers) of SiN_(x) orAlO_(x). PECVD SiN_(x) or AlO_(x) also provides H passivation of the 3-DTFSC substrate. In one embodiment, the diffusion/oxidation steps resultin selective emitter junction and emitter contact sheet resistancevalues of 80-150 Ω/square and 10-70 Ω/square, respectively. Step 1410involves self-aligned metallization (application of a metal coat). Thetop portions of the substrate is selectively coated (to a height equalto or less than the dopant source layer; in one embodiment, between 5and 20 microns) with metal (in one embodiment, silver) paste or liquidusing self-aligned liquid-dip coating, roller coating, inkjet coating,or spray coating. Next, this metal coat is dried and cured. Next, therear portions of the TFSC substrate are selectively coated (to a heightequal to or less than the rear cap dielectric layer) with metal (in oneembodiment, aluminum) to form p⁺⁺ base contact and metallization)paste/liquid by self-aligned liquid-dip coating, roller coating, inkjetcoating, or spray coating. Next, these metal coatings are dried andcured. Step 1412 involves self-aligned metallization (fire-through). Thecell front (e.g., silver) and rear (aluminum) metallized regions areformed by firing through the passivation layer or layer stack (oxideand/or PVD or PECVD SiN_(x) layers). Step 1414 involves an optionalself-aligned metallization step in which silver and/or copper isselectively/concurrently deposited (e.g., 1 to 5 microns) on themetallized top honeycomb ridges (emitter) and rear honeycomb ridges(base) by plating (such as electroless plating or galvanic plating),with further flash coating of the metallized regions with silver. Ifdesired, the plating process may also include an initial layer of arefractory metal barrier such as nickel (prior to silver and/or copperplating). Step 1416 involves another optional self-aligned metallizationstep. A forming gas anneal (FGA) is performed (e.g., at 300° C. to 450°C.) to reduce front and rear interconnect resistance values and helpwith surface/bulk passivation. This forming gas annealing step may notbe needed due to the prior metallization firing step. Step 1418 involvesmounting dual-aperture honeycomb-prism TFSC rear side (base side) onto ahighly reflective rear mirror. This rear mirror may be a diffuse mirrorwith a rough surface or specular with a smooth surface (a diffuse mirroris usually preferred). The rear mirror may be made of an silver-coatedaluminum or copper pad (foil) and may also serve as the TFSC baseinterconnect plane on a printed-circuit board placed in a solar moduleassembly. In step 1420, the honeycomb prism TFSCs are packaged in solarmodule assembly.

FIG. 113 shows an alternative process flow 1430 for fabricatingdual-aperture hexagonal-prism 3-D TFSCs without rear base layers. Exceptfor the order of the optional FGA and optional plating processes in theflow, the process flows of FIGS. 112 and 113 are otherwise similar andcomparable. Specifically, steps 1432 to 1442 in FIG. 113 are comparableto steps 1402 to 1412 in FIG. 112. For a description of steps 1432 to1442, see the descriptions above for steps 1402 to 1442 for FIG. 112.Step 1444 in FIG. 113 involves the optional FGA, before step 1446 whichinvolves the optional plating process. For a description of step 1414,see the description above for step 1416 of FIG. 112. For a descriptionof step 1446, see the description above for step 1414 of FIG. 112.

FIG. 114 shows an alternative process flow 1460 for fabricatingdual-aperture hexagonal-prism 3-D TFSCs without rear base layers. Theprocess flow of this embodiment uses a fire-through metallizationprocess to form the self-aligned emitter and base contact metallization.This flowchart describes the process flow for fabrication ofhexagonal-prism 3-D TFSCs using self-aligned fire-through metallizationwith boron-doped p⁺⁺ rear base contacts as well as phosphorus-doped n⁺⁺emitter contacts (including selective emitter doping on the 3-D prismsidewalls). While the p⁺⁺ base contacts in the embodiments of FIGS. 112and 113 are formed by aluminum doping during fire-through metallization,as mentioned above, the p⁺⁺ base contacts in the embodiment of FIG. 114are formed by boron doping from a cured boron source layer. Step 1462(providing a substrate) of FIG. 114 corresponds to step 1402 of FIG.112. Step 1464 involves selectively coating the top and rear portions ofthe 3-D honeycomb-prisms (in one embodiment, the top and rear 2 to 10microns) with phosphorus (i.e., n-type dopant) liquid/paste source ontop as well as boron (i.e., p-type dopant) and undoped dielectric (e.g.,oxide) liquid/paste sources on rear (boron layer capped by dielectricsealant such as oxide). This selective coating may be done usingself-aligned 2-sided roller coating using paste/liquid sources,liquid-dip coating by dipping in a controlled liquid source depth,ink-jet coating, or spray coating. Next, the dopant source layers anddielectric (oxide) cap layer are dried and cured (250° C. to 400° C.thermal curing or UV). Step 1466 involves formation of self-alignedselective emitter junction as well as the heavily doped emitter and basecontact diffusion regions. The top n⁺⁺p emitter contact diffusion andhoneycomb-prism sidewall n⁺p selective emitter junctions as well as rearp⁺⁺ base contacts are concurrently formed by thermal anneal (e.g., at800° C. to 950° C.). Drying/curing and emitter anneal may both beperformed sequentially in a diffusion or in-line belt-driven furnace. Inone embodiment, the 3-D TFSC substrate, or stacks of 3-D TFSC substratesin face-to-face contact, may be annealed while placed in a diffusionfurnace, in order to facilitate gas-phase doping formation of n⁺selective emitter junctions. The rear cap dielectric (e.g., oxide) layerprevents boron counter doping of selective emitter prism sidewalls. Step1468 (surface passivation and ARC) corresponds to step 1438 in FIG. 113;step 1470 (metal coat) corresponds to step 1440; step 1472 (firethrough) corresponds to steps 1442; step 1474 (FGA) corresponds to step1444; step 1476 (plating) corresponds to step 1446; step 1478 (mounting)corresponds to step 1448; and step 1480 (proceeding with packaging)corresponds to step 1450.

FIGS. 115 through 117 show additional alternative process flowembodiments 1490, 1520, and 1550 for fabricating dual-aperturehexagonal-prism 3-D TFSCs without rear base layers. While the processflow embodiments of FIGS. 112 to 114 use a fire-through metallizationprocess to form the emitter and base contact metallization regions (andin FIGS. 112 and 113 also to form the p⁺⁺ heavily doped base contactregions), the process flow embodiments of FIGS. 115 to 117 employselective plating (electroplating and/or electroless plating and/orgalvanic plating) to selectively form the emitter and base contactmetallization regions. Thus, the process flows outlined in FIGS. 115 to117 eliminate the need for a medium or high-temperature (e.g., 700° C.to 850° C.) fire-through metallization process and can result inimproved metallization contacts with reduced dark current and junctionleakage.

All of the fabrication process flow embodiments of FIGS. 112 to 117result in dual-aperture hexagonal-prism 3-D TFSCs without rear baselayers and with rear diffuse or specular reflective mirrors. The rearmirrors may be metal (e.g., silver-coated copper or silver-coatedaluminum) pads on thin printed-circuit boards used for assembling TFSCsinto packaged solar modules.

FIG. 115 shows an alternative process flow 1490. Step 1492 (providing asubstrate) corresponds to step 1462 of FIG. 114; step 1494 (selectivecoating) corresponds to step 1464; step 1496 (self-aligned selectiveemitter) corresponds to step 1466; and step 1498 (surface passivationand ARC) corresponds to step 1468. Step 1500 involves self-alignedmetallization etching. The top and rear portions of the honeycomb prismsare selectively coated (to heights equal to or less than the n-type andp-type dopant source layers, respectively) with dielectric etchantliquid or paste layers. This dielectric etchant coating may be done byself-aligned single-sided or double-sided roller coating usingpaste/liquid sources, liquid-dip coating by dipping in a specifiedliquid etchant source depth, ink-jet coating, or spray coating. Thisetching step strips, to controlled heights, dielectric layer or layerstack (e.g., oxide or oxide/nitride) from top and rear portions ofhoneycomb prisms to expose silicon. Next, the TFSC substrate is rinsedand subsequently dried. Step 1502 involves self-aligned metallization(using electroless plating, galvanic plating, or electroplating). Theexposed front and rear emitter and base metallized regions areconcurrently formed using selective electroplating and/or electrolessplating to form a single layer or multiple layers of high-conductivitymetallized regions. Embodiments include silver, aluminum, nickel,titanium, cobalt, or tantalum. For instance, the plated metal stack mayinclude a thin (50 to 500 nanometers) barrier and adhesion layer such asnickel (nickel) followed by a relatively thick (2 to 15 microns) layerof high-conductivity metal (silver or copper or aluminum). If ahigh-conductivity metal other than silver is used for the thickmetallization layer, a final flash coat of silver may be used to createa high-reflectivity surface coating in order to improve light reflectionand trapping into the 3-D cells (by the emitter metallization contact).Step 1504 (optional FGA) corresponds to step 1474 of FIG. 114; step 1506(optional plating) corresponds to step 1476; step 1508 (mounting)corresponds to step 1478; and step 1510 (proceeding with module assemblyand packaging) corresponds to step 1480.

FIG. 116 shows an alternative process flow 1520. Step 1522 (providing asubstrate) corresponds to step 1492 of FIG. 115; step 1524 (selectivecoating) corresponds to step 1494; and step 1526 (self-aligned selectiveemitter) corresponds to step 1496. Step 1528 involves surfacepassivation thermal oxidation. A thermal oxide layer is grown, in oneembodiment by steam oxidation. In one embodiment, this layer is between5 and 300 nanometers (preferably 10 to 50 nanometers), with theoxidation performed at 800° C. to 950° C. (lower temperatures andthinner oxides preferred). Alternatively, this step may be merged intothe prior diffusion step in the diffusion furnace, to be performedsequentially in a multi-zone in-line diffusion furnace after theselective emitter and base diffusion step. In one embodiment, thecombined thermal budget associated with the diffusion and thermaloxidation steps results in 3-D honeycomb-prism selective emitter andheavily-doped emitter contact sheet resistance values of 80-150 Ω/squareand 10-70 Ω/square, respectively. Step 1530 involves self-alignedmetallization (etching). The 3-D TFSC substrate is covered with thecured dopant source layers on top (emitter side) and rear (base side)and an undoped dielectric cap (sealant such as cured oxide) layer onrear. The top and rear cured dielectric and solid dopant source portionsare selectively etched using a suitable dielectric etchant (e.g., anHF-based etchant) with relatively high selectivity with respect tothermal oxide. This selectively strips the cured dopant source segmentsand undoped capping (oxide) dielectric on the top and rear portions ofthe honeycomb prisms and exposes silicon in those regions, whileremoving only a small fraction of thermal oxide from honeycomb-prismsidewalls. Therefore, the honeycomb-prism sidewalls corresponding to theselective emitter regions and outside the emitter and base contactregions remain covered with thermal oxide. Step 1532 (plating)corresponds to step 1502 of FIG. 115; step 1534 (FGA) corresponds tostep 1504; step 1536 (plating) corresponds to step 1506; and step 1538(mounting) corresponds to step 1508. Step 1540 involves an optional stepof depositing a passivation and anti-reflection coating (ARC) layer(e.g., 50-200 nanometers of PVD or PECVD SiN_(x)) layer on mountedcells. Step 1542 (proceeding with packaging) corresponds to step 1510 ofFIG. 115.

FIG. 117 shows an alternative process flow 1550. Step 1552 (providing asubstrate) corresponds to step 1522 of FIG. 116. Step 1554 involvesselectively coating the top and rear portions of the 3-D substrate (inone embodiment, the top and rear 2 to 10 microns in height) with aphosphorus (i.e., n-type dopant) liquid/paste source on top and anundoped capping (sealant) dielectric such as oxide liquid/paste sourceon rear. This coating may be done by self-aligned single-sided or2-sided roller coating using liquid/paste sources, liquid-dip coating bydipping in a controlled liquid source depth, ink-jet coating, or spraycoating. Next, the dopant and capping dielectric (oxide) layers aredried and cured (e.g., using thermal curing at 250° C. to 400° C. or byUV irradiation). Step 1556 (self-aligned selective emitter) correspondsto step 1526 of FIG. 116. Step 1558 (surface passivation and ARC)corresponds to step 1498 of FIG. 115. Step 1560 involves selectivelyetching the top and rear portions of the cells in preparation forself-aligned metallization The top and rear portions of the honeycombprisms (to heights equal to or less than the n-type and p-type dopantsource layers, respectively) are selectively coated with dielectricetchant liquid or paste layers. This coating may be done by self-alignedsingle-sided or double-sided roller coating using paste/liquid sources,liquid-dip coating by dipping in a specified liquid etchant sourcedepth, ink-jet coating, or spray coating) to strip controlled heights ofoxide/nitride dielectrics from top and rear portions of honeycomb prismsto expose silicon at the honeycomb ridges. Next, the TFSC substrate isrinsed and dried. Step 1562 involves self-aligned metallization (in oneembodiment, using plating). The rear base aluminum metallized regionsare formed by selective electroplating or electroless plating. Thisaluminum plating process may be limited to the rear base regions. Step1564 involves self-aligned metallization (anneal). The substrate goesthrough an annealing or firing process to form rear aluminum-doped p⁺base contacts. Then, an optional forming gas anneal (FGA) is performed(e.g., 350° C. to 450° C.) to reduce interconnect resistance and helpwith surface/bulk passivation. Step 1566 involves self-alignedmetallization (plating). A high-conductivity metal (such as silver orcopper) (e.g., 2 to 12 microns) is selectively/concurrently deposited onthe top honeycomb ridges (emitter) and rear honeycomb ridges (aluminummetallized base contacts) by plating. If necessary, a suitable thin(e.g., 50 to 200 nanometers) refractory metal barrier layer such asnickel is first selectively deposited by plating (in one embodiment,electroless plating) before depositing the silver or copper layer. Next,if necessary, the TFSC substrate may be flash coated with a thin layerof high-reflectivity silver (not needed if the thick metallization layeris also silver). Alternatively, this may be merged into the priorplating step. Step 1568 (mounting) corresponds to step 1538 of FIG. 116;step 1570 (proceeding with packaging) corresponds to step 1542.

The above process steps may be performed on integrated belt-drivenprocess equipment, as shown in FIGS. 21 through 23 above.

FIG. 118A shows a Y-Y cross-sectional view 1600 of a self-supportinghexagonal-prism dual-aperture 3-D TFSC substrate with a thin siliconframe 1602 and without a rear base layer, before TFSC fabrication. Inthis embodiment, the thin silicon frame 1602 is square-shaped with thesame thickness as 3-D TFSC substrate, with a silicon frame width 104 of50 to 250 microns. The final 3-D TFSC substrate is may be square-shaped,with dimensions ranging from roughly 125 mm×125 mm to greater than 200mm×200 mm.

FIG. 118B shows a view 1610 of the substrate of FIG. 118A after TFSCfabrication, indicating the emitter and base metal contacts for thehexagonal-prism 3-D TFSC without a thick silicon frame. The thin siliconframe also shows the wrap-around (may be made wrap through instead)emitter contact metal for ease of module assembly (making the cellemitter and base contacts to the module from the cell backside). Thethin silicon frame extension may be made during the 3-D substratefabrication process. For example, the thin frame may be made by thesilicon deposition process as the hexagonal-prism structure is formed inthe template. A self-aligned peripheral frontside contact 1612 isconnected to the 3-D TFSC hexagonal frontside emitter contact at theframe edge (connected to the distributed self-aligned emitter contact1614). The self-aligned emitter contact 1614 may be formed by rollercoating, liquid-dip coating, or spray-jet-coating and fired through thepassivation layer (nitride or oxide/nitride stack). Alternatively, theself-aligned emitter contact 1614 may be formed using a selectiveplating process. A self-aligned wrap-around emitter contact is on thethin silicon frame (the wrap-around contact may be replaced with awrap-through contact). Both frontside and backside contacts areaccessible on the rear side of the cell for automated module assembly.

FIG. 119A shows a Y-Y cross-sectional view 1620 of a self-supportinghexagonal-prism dual-aperture 3-D TFSC substrate with a thick peripheralsilicon frame 1622. FIG. 119B shows a view 1630 of the substrate of FIG.119A after cell fabrication, indicating the emitter and base metalcontact metals. The thick-Si frame also shows the self-alignedwrap-around emitter contact metal 1612 (on thick silicon frame 1622) forease of module assembly (the wrap-around contact may be replaced with awrap-through contact). The thick silicon frame may be separately made oflow-cost silicon wafers (e.g., laser cut from wafers) and then attachedto the hexagonal prism 3-D TFSC substrate by a suitable technique. Forexample attachment may occur during the epitaxial silicon depositionprocess, to seal the frame to the hexagonal-prism structure, or byelectron-beam welding, etc. The hexagonal-prism 3-D TFSC fabricationprocess flows of this disclosure utilize roller coating, spray coatingor liquid-dip coating followed by thermal or UV curing for self-alignedformation of solid dopant layers and metal layers (the latter for thecell fabrication process flow embodiments using fire-throughmetallization). In one of the process flow embodiments, a roller coating(or spray coating or liquid-dip coating) process may also be used forcontrolled dielectric etching from hexagonal ridges. Also shown are theself-aligned backside hexagonal base contacts 1632 (roller-coated,dip-ink-coated, or spray-jet-coated and fired through the passivationlayer such as nitride or oxide/nitride stack). Both frontside emittermetallization contact and backside base contact are accessible on therear side of the cell for automated module assembly.

FIG. 120 shows a schematic magnified top view 1640 of a regular(equilateral) hexagonal-prism 3-D TFSC substrate showing a plurality ofprism unit cells. Each hexagonal unit cell 106 contains hexagonal unitcell boundary points (H₁, H₂, H₃, H₄, H₅, and H₆) 152, 154, 156, 158,160, 162. FIG. 120 shows the hexagonal-prism 3-D TFSC substratesidewalls 144; the long diagonal dimension of the unit cell hexagon (d)164; and the short diagonal dimension of the hexagonal unit cell (h)166. In one embodiment, the hexagonal-prism 3-D TFSC substrate sidewalls144 are between 2 and 30 microns thick.

FIG. 121 shows a view 1650 of a hexagonal-prism dual-aperture 3-D TFSCsubstrate after release from a template where the hexagonal-prism 3-DTFSC substrate has both top (emitter) open apertures 142 and rear (base)apertures (not shown). The top ridges 144 are used for n⁺⁺ emitterdiffusion and contact metal, while the rear ridges 146 are used for p⁺⁺base diffusion and contact metal. FIG. 122A shows a Y-Y cross-sectionalview 1660 of a hexagonal prism 3-D TFSC substrate shown in FIG. 121.Note that the 3-D TFSC substrate has height 172 (typically a value inthe range of 100 to 350 microns). FIG. 122B shows a Z-Z cross-sectionalview 1670 of hexagonal-prism 3-D TFSC substrate shown in FIG. 121. Notethat the Z-Z view shows thin-film walls with width d/2 108 (compared tothe hexagonal aperture long diagonal diameter d).

FIGS. 123A to 127 show various representative dual-aperturehexagonal-prism 3-D TFSC structures (with tapered prism sidewalls). Oneembodiment uses crystalline silicon (c-Si) for the TFSCs; polysilicon,amorphous silicon, as well as non-Si absorbers may also be used inalternative embodiments. These TFSCs are fabricated based on the processembodiments described earlier in FIGS. 112-117. These cross-sectionalviews correspond to dual-aperture hexagonal-prism 3-D TFSCs without rearbase layers. The hexagonal prism 3-D TFSCs shown in these FIGURES havetapered prism sidewalls (in one embodiment, narrower emitter siliconwidth on the top and wider base silicon width at the bottom).

FIG. 123A shows a Y-Y cross-sectional view 1700 of a single unit cellwithin a dual-aperture hexagonal-prism 3-D TFSC without a rear baselayer, with tapered prism posts 1702. The central region 1704 of theprism post 1702 contains p-type silicon serving as the base region. Thecell view 1700 is after self-aligned formation of: heavily-doped emittercontact diffusion regions 1706 (e.g., more heavily-doped withphosphorus, n⁺⁺ doped emitter contact regions on the hexagonal prism tophexagonal ridges as shown); selective emitter regions 1708 (e.g., lessheavily-doped with phosphorus, n⁺ selective emitter on thehexagonal-prism sidewall surfaces as shown); and heavily-doped basecontact regions 1710 (e.g., more heavily-doped with boron, p⁺⁺ dopedbase contact regions on the hexagonal prism rear hexagonal ridges asshown). The hexagonal-prism sidewalls are in-situ-doped (at the time of3-D TFSC substrate fabrication) with boron (either uniformly or in agraded profile, more lightly doped at the prism sidewall surface andmore heavily doped towards the sidewall vertical center axis). The cellview 1700 is before formation of emitter and base contact metallization.Further, each sidewall 1702 has a top silicon thickness (T_(st)) 786 andbottom silicon thickness (T_(sb)) 790. Each sidewall has an off-normaltaper sidewall angle, θ 792.

Compared to the doping polarities shown in FIG. 123A, all the celldoping polarities may be inverted. FIG. 123B shows a view 1720 of thesame TFSC as in FIG. 123A but with inverted doping polarities (i.e.,n-type base and p-type emitter regions).

FIG. 123B shows a Y-Y cross-sectional view 1720 of a single unit cellwithin a dual-aperture hexagonal-prism 3-D TFSC without a rear baselayer, with tapered prism posts 1702. The central region 1722 of theprism post 1702 contains n-type silicon serving as the cell base region.The cell view 1720 is after self-aligned formation of: heavily-doped p⁺⁺emitter contact regions 1726; selective p⁺ selective emitter regions1726; and heavily-doped n⁺⁺ base contact regions 1728. The cell view1720 is before formation of emitter and base contact metallization.

Continuing from FIG. 123A, FIG. 124A shows a Y-Y cross-sectional view1730 of a unit cell within a hexagonal prism 3-D TFSC, with p-type prismposts 1702. The cell view 1730 is after self-aligned formation of:surface passivation oxide and anti-reflection coating (ARC) layer(s)1732; emitter contact metal 1734 (e.g., silver, copper, aluminum; usinga refractory metal barrier if necessary) with coverage height L_(em)1736 and base contact metal 1738 (silver, copper, aluminum; using arefractory metal barrier if necessary) with coverage height L_(bm) 1740by fire-through and/or selective plating. The hexagonal-prism sidewallsare in-situ-doped (at the time of 3-D TFSC substrate fabrication) withboron (either uniformly or in a graded profile, more lightly doped atthe prism sidewall surface and more heavily doped towards the sidewallvertical center axis). The cell view is before mounting the cells onto ahighly reflective rear mirror.

As noted above, all the cell doping polarities may be inverted.Continuing from FIG. 123B, FIG. 124B shows a Y-Y cross-sectional view1750 of a unit cell within a dual-aperture hexagonal-prism 3-D TFSC,with n-type prism posts 1722. All the cell doping polarities areopposite of those shown in FIG. 124A. The cell view 1750 is afterself-aligned formation of: surface passivation oxide and anti-reflectioncoating (ARC) layer(s) 1732; emitter contact metal 1734 (silver, copper,aluminum; using a refractory metal barrier if necessary) with coverageheight L_(em) 1736 and base contact metal 1738 (silver, copper,aluminum; using a refractory metal barrier if necessary) with coverageheight L_(bm) 1740 by fire-through and/or selective plating. Thehexagonal-prism sidewalls are in-situ-doped (at the time of 3-D TFSCsubstrate fabrication) with phosphorus (either uniformly or in a gradedprofile, more lightly doped at the prism sidewall surface and moreheavily doped towards the sidewall vertical center axis). The cell viewis before mounting the cells onto a highly reflective rear mirror.

Continuing from FIG. 124A, FIG. 125A shows a Y-Y cross-sectional view1760 of a unit cell after mounting the cell onto a detached highlyreflective rear specular mirror 572 with a polished mirror surface. Adetached mirror is not integrated through direct material deposition onthe cell. In one embodiment, the mirror is made of silver and/oraluminum (or a polished disk coated with silver and/or aluminum and/orAu), with reflectance greater than 95% for λ between 800 and 1200nanometers. The rear mirror surface to base contact spacing (S) 604 maybe in the range of 0 (i.e., direct contact between the rear mirror andthe hexagonal base contact; in this case the rear mirror also serves asthe base electrical interconnect plane) up to roughly H (or a spacing asmuch as the height of the hexagonal prism cell—up to 100 to 500microns).

Continuing from FIG. 124B, FIG. 125B shows a Y-Y cross-sectional view1770 of a unit cell after mounting the cell onto a highly reflectiverear diffuse mirror 602 with textured mirror surface. In one embodiment,the mirror is silver-coated, with reflectivity greater than 95% for λbetween 800 and 1200 nanometers.

FIG. 126A shows a cross-sectional view 1780 of several prism unit cellsfrom the hexagonal-prism TFSC shown in FIG. 125A.

FIG. 126B shows a cross-sectional view 1790 of several prism unit cellsfrom the hexagonal-prism TFSC shown in FIG. 125B.

FIG. 127 shows a cross-sectional view 1800 of the hexagonal prism TFSCabove, mounted on and in contact with a detached diffuse (rough)high-reflectivity rear mirror 602 (made of silver and/or aluminum and/orAu or their coatings). The rear mirror surface to base contact spacing(S) depicted here is zero and, thus, there is direct contact between therear diffuse mirror and the cell base contact metal. Therefore, the rearmirror also serves as the base electrical interconnect plane. The rearmirror may be part of the solar module assembly (e.g., a printed-circuitboard with silver-coated copper interconnects connecting to the cellemitter and base contact metallization and connecting the cells inseries). This FIGURE shows several prism unit cells and corresponds tothe same hexagonal-prism TFSC shown in FIG. 125B but with a zeromirror-to-base contact spacing 604 (FIG. 125B shows one unit cell).

FIGS. 123A to 127 show 3-D TFSCs of this disclosure with tapered prismsidewalls. It is also possible to fabricate hexagonal-prism 3-D TFSCs(with or without rear base layers) which have substantially verticalprism sidewalls. For example, FIG. 128A shows a Y-Y cross-sectional viewof a unit cell. Except for the sidewall profile (being vertical), othercell design features are essentially similar to those of thetapered-wall cell shown in FIG. 123A. Note the uniform hexagonal wallthickness (T_(s)) 1812 compared to FIG. 123A.

Continuing from FIG. 128A, FIG. 128B shows a Y-Y cross-sectional view1820 of a unit cell. Except for the sidewall profile (being vertical),other cell features are essentially similar to those of the tapered-wallcell shown in FIG. 123A. Note L_(tm) 1822 compared to FIG. 123A.

Continuing from FIG. 128B, FIG. 129 shows a Y-Y cross-sectional view1830 of a unit cell after mounting the cell onto a reflective specularrear mirror 572. This hexagonal prism cell has vertical prism sidewalls(i.e., equal top emitter and rear base prism sidewall widths). Exceptfor the sidewall profile (being vertical), other cell features areessentially similar to those of the tapered-wall cell shown in FIG.125A. Again, note L_(tm) 1822 and the uniform hexagonal wall thickness(T_(s)) 1812.

Again continuing from FIG. 128B, FIG. 130 shows a Y-Y cross-sectionalview 1840 of a unit cell after mounting the cell onto a diffuse rearmirror 602. This hexagonal prism cell has vertical prism sidewalls(i.e., equal top emitter and rear base prism sidewall widths). Exceptfor the sidewall profile (being vertical), other cell features aresimilar to those of the tapered-wall cell shown in FIG. 125B. Again,note L_(tm) 1822 and the uniform hexagonal wall thickness (T_(s)) 1812.

FIG. 131 shows a Y-Y cross-sectional view 1850 of a dual-aperturehexagonal-prism 3-D TFSC with vertical prism sidewalls and without aflat base layer, mounted on a detached specular high-reflectivity rearmirror 572 (made of silver and/or aluminum and/or Au or their coatings).The rear mirror surface to base contact spacing (S) 604 may be in therange of 0 (i.e., direct contact between the rear mirror and the basecontact; in this case the rear mirror also serves as the baseinterconnect plane) up to roughly H (or a spacing as much as the heightof the hexagonal prism cell). This FIGURE shows several prism unit cellsand corresponds to the same hexagonal-prism cell shown in FIG. 129(which shows one unit cell).

FIG. 132 shows a Y-Y cross-sectional view 1860 of a dual-aperturehexagonal-prism 3-D TFSC with vertical prism sidewalls and without aflat base layer, mounted on a detached diffuse high-reflectivity rearmirror 602 (made of silver and/or aluminum and/or Au or their coatings).The rear mirror surface to base contact spacing (S) 604 may be in therange of zero (i.e., direct contact between the rear mirror and the basecontact; in this case the rear mirror also serves as the baseinterconnect plane) up to roughly H (or a spacing as much as the heightof the hexagonal prism cell). This FIGURE shows several prism unit cellsand corresponds to the same hexagonal prism cell shown in FIG. 130(which shows one unit cell).

One of the important features of the hexagonal-prism 3-D TFSCs of thisdisclosure (both with and without rear base layers) is highly efficientcollection of photogenerated carriers due to the unique devicestructure. For instance, the selective emitter junctions cover bothsurfaces of the prism sidewalls. Therefore, in the case ofhexagonal-prism 3-D TFSCs with n⁺ selective emitter junctions andin-situ-boron-doped starting hexagonal-prism 3-D TFSC substrates, anyphotogenerated electrons in the prism sidewalls are efficientlycollected by the selective emitter junctions that cover both surfaces ofthe prism sidewalls. This makes the cells of this disclosure lessdemanding in terms of substrate defects or minority carrier diffusionlength.

A minority carrier diffusion length just a few times larger than theprism sidewall thickness (e.g., by a factor of 2 to 5) providessufficient material quality for effective collection of thephotogenerated carriers with negligible recombination losses by one ofthe two selective emitter junctions located nearby in the adjacentsidewall surfaces. For instance, for a prism sidewall silicon filmthickness of 5 microns, a minority carrier diffusion length of greaterthan 10 to 15 microns should provide sufficient substrate lifetimequality for achieving ultra-high cell efficiency due to minimalrecombination losses. This is a key advantage compared to the currentsilicon wafer solar cells, where the photogenerated carriers may have totravel as far as 150 to 200 microns to be collected (thus, requiring aminority carrier diffusion length of at least hundreds of micrometers).As a result of this key advantage, it is possible to fabricatehigh-performance hexagonal-prism 3-D TFSCs based on the embodiments anddesigns of this disclosure (and their many derivatives) using apolycrystalline semiconductor absorber such as multicrystalline siliconor polysilicon, instead of the more expensive monocrystalline silicon.

FIGS. 133A and 133B show an enlarged views of a hexagonal-prism unitcell in a hexagonal-prism 3-D TFSC of this disclosure, both before andafter cell fabrication (shown before and after self-aligned cellmetallization).

FIG. 133A shows a quasi 3-D view 1870 of a single unit cell from aregular dual-aperture hexagonal-prism TFSC of this disclosure (shown forthe cell without a rear base layer), before self-aligned base andemitter contact metallization. The prism sidewall surfaces are doped toform the selective emitter junctions (e.g., n⁺p junctions in boron-dopedsilicon base). This FIGURE corresponds to the cell fabrication processflow embodiments in FIGS. 112-117. FIG. 133A shows top hexagonal opening144, which may form the frontside self-aligned emitter metallizationcontacts 502; and rear (bottom) hexagonal opening 146, which may formthe rear selective base self-aligned contacts 504. Refer back to FIG.24.

FIG. 133B shows a quasi 3-D view 1880 of a single unit cell from aregular hexagonal prism TFSC of this disclosure, after cell fabrication,including self-aligned base and emitter contact metallization. The darkregion on the top of the unit cell is the self-aligned emitter contactmetal 502; the rear of the unit cell is the self-aligned base contactmetal 504. The prism sidewall surfaces are doped to form the selectiveemitter junctions (e.g., shallow n⁺p junctions with a junction depth of0.2 to 0.5 micron in boron-doped silicon base).

FIG. 134 shows a partial view 1890 of multiple adjacent prism unit cells(compared to a single unit cell in FIG. 133B) after mounting the cellrear base side (base contact metal regions 504) onto a rear mirror 1892(specular 572 or diffuse rear mirror 602, as shown in previous FIGURES).The rear mirror 1892 may be made of a suitable planar material (e.g.,copper or aluminum) flash-coated with silver or aluminum (e.g., usingplating). The rear mirror may be copper interconnect pads or islands(plated with silver and/or aluminum) on a printed-circuit board (PCB)within a solar module assembly. Thus, the rear mirrors may also serve asbase electrical interconnect planes. The rear base contact metal regions504 may be soldered or glued (or simply placed) onto the plated copperpads on the solar module PCB assembly. There is an optional step ofsilver flash coating of the assembled module structure to coat thesolder joint surfaces with optically reflective silver (silver).

The templates described above may be used to fabricate 3-D TFSCsubstrates for use in 3-D TFSCs. FIGS. 135 through 141 show variousembodiments of hexagonal-prism 3-D TFSC substrate fabrication processflows for fabricating hexagonal-prism (or other prism-array shapes)dual-aperture 3-D TFSC substrates without rear base layers based on theuse of templates described earlier. All of the embodiments shown inFIGS. 135 through 141 use sacrificial layer formation (e.g., poroussilicon sacrificial layer) and trench-fill deposition processes (e.g.,epitaxial silicon deposition) which may be highly conformal, forconformal formation of the sacrificial (porous silicon) layer andsubsequent seamless void-free filling of the trenches with asemiconductor absorber layer such as in-situ-doped (e.g., in-situ borondoped) monocrystalline or multicrystalline silicon layer. One embodimentuses a patterned single-crystal (monocrystalline) silicon ormulticrystalline silicon (mc-Si) square-shaped (or round) template, withdimensions of approximately 150 mm×150 mm to over 200 mm×200 mm.Alternative embodiments may use much lower cost metallurgical-grade orsolar-grade silicon.

FIG. 135 shows an embodiment of a process flow 1900 for fabrication ofself-supporting (free standing) hexagonal-prism 3-D TFSC substratesusing layer release processing. This process flow results indual-aperture hexagonal-prism 3-D TFSC substrates with hexagonal prismswith open apertures formed on both the top and rear (there is no rearbase layer). In step 1902, a patterned hexagonal-prism (or another prismarray) template is provided. This template has already been processed toform an embedded array of deep hexagonal-prism trenches. There is apatterned dielectric (oxide and/or nitride) hard mask on the templatetop and rear surfaces. Step 1904 involves a multi-layer blanketepitaxial semiconductor deposition in an epitaxial growth reactor. Step1904 first involves an H₂ or GeH₄/H₂ in-situ bake cleaning, which isperformed after a standard pre-epitaxial wet clean (the latter ifnecessary). Next, a thin sacrificial epitaxial layer is deposited on thefrontside only. In one embodiment, Ge_(x)Si_(1-x) is used for thesacrificial epitaxial layer and is between 10 and 2000 nanometers (inanother embodiment a layer of porous silicon is directly deposited forthe sacrificial layer). Next, a doped monocrystalline silicon epitaxiallayer is deposited (in one embodiment, on the frontside only). In oneembodiment, the layer is p-type, boron-doped and has a thickness between1 and 30 microns. Step 1906 involves selective silicon etch toselectively strip the top silicon layer, stopping on the sacrificiallayer. First, the top silicon layer is removed using a selective (wet ordry) silicon etch process until the top Ge_(x)Si_(1-x) epitaxial layer(or porous silicon) or oxide/nitride hard mask is exposed. When using aplasma (dry) etch process, one embodiment uses optical end-pointdetection to ensure complete removal of the top silicon layer andexposure of the top sacrificial (Ge_(x)Si_(1-x) or porous silicon)layer. Step 1908 involves 3-D TFSC substrate release using a selectiveetchant to etch the sacrificial layer. A highly selective isotropic (inone embodiment, wet) etch of Ge_(x)Si_(1-x) is performed, with very highselectivity with respect to silicon (in one embodiment, with etchselectivity much better than 100:1). In one embodiment, a mixture ofhydrofluoric acid, nitric acid and acetic acid (HNA) is used to etch thesacrificial Ge_(x)Si_(1-x) layer (etchants such as H₂O₂+H₂O or TMAH maybe used to selectively etch porous silicon). Alternatively, a mixture ofammonia, peroxide, and water (NH₄OH+H₂O₂+H₂O) may be used. This processreleases the crystalline silicon layer as a hexagonal-prism 3-D TFSCsubstrate, which may then be used for subsequent 3-D TFSC fabrication.

FIG. 136 shows a process flow 1910 of an embodiment of a process flowfor fabrication of self-supporting hexagonal-prism dual-aperture 3-DTFSC substrates using layer release processing. This process flowresults in hexagonal-prism 3-D TFSC substrates comprisinghexagonal-prisms with open apertures formed on both the 3-D TFSCsubstrate top and rear (there is no rear base layer). In step 1912, apatterned hexagonal-prism template is provided. This template hasalready been processed to form an embedded array of deep trenches asdescribed before. In this case, there are no dielectric hard mask layerson the template top and rear surfaces. Step 1914 (multi-layer blanketepitaxial deposition) corresponds to step 1904 in FIG. 135; step 1916(selective silicon etch) corresponds to step 1906; step 1918 (substraterelease) corresponds to step 1908. The resulting hexagonal-prism 3-DTFSC substrate may then be used for subsequent 3-D TFSC fabrication.

In the process flows described in FIGS. 135 and 136, while crystallineGe_(x)Si_(1-x) is used as a sacrificial layer between the template andthe in-situ-doped epitaxial silicon layer, other suitable sacrificiallayers may be used. Alternative suitable materials include crystallineporous silicon (embodiments include microporous or mesoporous silicon),crystalline GeSiC, or SiC, among others. In the embodiments which useGe_(x)Si_(1-x) as the sacrificial layer, the Ge_(x)Si_(1-x) layer ispreferably between 50 nanometers and 3 microns thick, and morepreferably between 0.1 and 1 micron. The germanium mole fraction (x) inthe sacrificial layer is preferably between x=10% to x=45%, and morepreferably between x=25% to x=40% in order o provide sufficient etchselectivity with respect to silicon. The germanium mole fraction shouldbe high enough to achieve an acceptable high etch selectivity forremoval of the Ge_(x)Si_(1-x) layer with minimal etching of silicon,while low enough to produce high-quality epitaxial silicon withsufficiently low defect density over the Ge_(x)Si_(1-x) sacrificiallayer. The sacrificial layer may have a fixed germanium mole fractionthroughout the sacrificial Ge_(x)Si_(1-x) layer or may also have gradedmole fraction transition regions between the Ge_(x)Si_(1-x) layer andthe template as well as between the Ge_(x)Si_(1-x) layer and the topin-situ-doped epitaxial silicon layer. Graded mole fraction transitionregions result in a trapezoidal germanium mole fraction profile, firstincreasing from an x of 0% to an x of between 25% and 40% in the firsttransition region next to the template, then a Ge_(x)Si_(1-x) regionwith a fixed x between 25% and 40%, and a second transition region withx decreasing from an x of 40% to an x of 0% under the in-situ-dopedepitaxial silicon layer. The transition regions with graded x and themiddle layer with a fixed x may each be roughly between 10 nanometersand 1 micron thick.

Depending on the emitter doping type (n-type or p-type), the in-situbase doping type is chosen to be p-type (e.g., boron) or n-type (e.g.,phosphorus). The embodiments shown in FIGS. 135 and 136 provide examplesof boron-doped hexagonal prism 3-D TFSC substrates which may be used tofabricate TFSCs with n-type, phosphorus-doped selective emitters. In analternative embodiment, all the doping polarities may be inverted,resulting in phosphorus-doped hexagonal-prism 3-D TFSC substrates whichmay be used for fabricating cells with boron-doped selective emitters.

FIGS. 135 through 137 show embodiments of process flows which utilizeGe_(x)Si_(1-x) as the sacrificial layer between the template and theepitaxial silicon TFSC substrate. FIGS. 135 and 136 depict embodimentsof process flows which utilize blanket epitaxial silicon deposition aspart of the process flow. On the other hand, FIG. 137 shows analternative embodiment of a process flow 1920 using selective epitaxialsilicon deposition and layer release processing. The resulting 3-Ddual-aperture TFSC substrates of FIG. 137 have open apertures on bothsubstrate top and rear. In step 1922, a patterned hexagonal-prismtemplate is provided. This template has already been processed to forman embedded array of deep trenches. There is a patterned dielectricoxide and/or nitride (and/or another suitable dielectric such asdiamond-like carbon or DLC, thin-film diamond, etc.) hard mask on thetemplate top surfaces. Step 1924 (multi-layer blanket epitaxy)corresponds to step 1904 in FIG. 136. Note, however, that both theGe_(x)Si_(1-x) sacrificial layer and the epitaxial silicon layer areselectively grown inside the trenches only. No layer is grown on thetemplate top dielectric layer due to selective epitaxy (there is apatterned dielectric hard mask on top, such as oxide, nitride, DLC,etc.). Step 1926 (substrate release) corresponds to step 1918 in FIG.137. The hexagonal-prism 3-D TFSC substrate may then be used forsubsequent 3-D TFSC fabrication.

FIG. 138 depicts a process flow 1930 of an embodiment of a process flowfor fabrication of self-supporting hexagonal-prism 3-D dual-apertureTFSC substrates without rear base layers using layer release processing.Process flow 1930 uses monocrystalline or quasi-monocrystalline porous(microporous or mesoporous) silicon (instead of Ge_(x)Si_(1-x)) as thesacrificial layer, and blanket epitaxial silicon fill. The dual-aperturehexagonal-prisms have open apertures on both top and rear. Step 1932(providing a substrate) corresponds to step 1922 in FIG. 137. Step 1934involves forming a thin porous silicon sacrificial layer on templatedeep trenches (trench sidewalls and bottoms) using electrochemical HFetching (also known as electrochemical anodization of silicon). Theporous silicon layer may be formed by one of two primary techniques asfollows: (i) deposit a thin conformal crystalline silicon layer (in oneembodiment, a p-type boron-doped silicon layer in the range of 0.2 to 2microns) on an n-type template substrate, using silicon epitaxy,followed by conversion of the p-type epitaxial layer to porous siliconusing electrochemical HF etching; or (ii) convert a thin layer of thetemplate substrate (in one embodiment, a p-type template) to poroussilicon (in one embodiment, in the thickness range of 0.01 to 1 micron).The sacrificial porous silicon formed by one of these two techniquesalso serves as a seed layer for subsequent epitaxial silicon deposition.Step 1936 involves performing a hydrogen bake (at 950° to 1150° C.) toclean the surface and to form a continuous sealed monocrystallinesurface layer on the surface of the porous silicon sacrificial layer,followed by depositing a blanket layer of doped silicon epitaxy (toponly) in an epitaxial processing reactor. In one embodiment, the layeris p-type, boron-doped and has a thickness between 1 and 30 microns.Step 1938 uses a selective (wet or dry) silicon etch process to stripthe top silicon layer, until the top layer of porous silicon is exposed.When using a plasma (dry) etch process, one embodiment uses opticalend-pointing to ensure complete removal of top silicon layer andexposure of the top porous silicon layer. Step 1940 involves 3-D TFSCsubstrate release. A highly selective isotropic wet or dry etch ofporous silicon is performed, with very high selectivity with respect tosilicon. In one embodiment, a mixture of hydrofluoric acid, nitric acidand acetic acid (HNA) is used to etch the porous silicon layer.Alternatively, a mixture of ammonia, peroxide, and water(NH₄OH+H₂O₂+H₂O) or a mixture of hydrogen peroxide and hydrofluoric acid(H₂O₂+HF) or a suitable composition of tri-methyl-ammonium-hydroxide(TMAH) may be used. The etch composition and temperature may be adjustedto achieve maximum etch selectivity for porous silicon with respect tosilicon. This process releases the embedded 3-D crystalline siliconstructure as a hexagonal-prism 3-D TFSC substrate, which may then beused for subsequent 3-D TFSC fabrication.

FIG. 139 depicts a process flow 1950 of an embodiment of a process flowfor fabrication of self-supporting dual-aperture hexagonal-prism 3-DTFSC substrates without rear base layers using a porous siliconsacrificial layer and selective epitaxial silicon deposition. The maindifference between FIGS. 138 and 139 is the epitaxial growth method.FIG. 139 uses selective epitaxy instead of blanket epitaxy as in FIG.138. The use of selective epitaxy eliminates a process step to etch thetop silicon layer before removal of the sacrificial layer for layerrelease. Referring to FIG. 139, step 1952 (providing a substrate)corresponds to step 1932 in FIG. 138; and step 1954 (formation of poroussilicon sacrificial layer) corresponds to step 1934. In step 1956,epitaxial silicon is selectively grown inside the template trenchesonly. In one embodiment, the epitaxial silicon layer is p-type,in-situ-boron-doped and has a thickness between 1 and 30 microns. Nosilicon layer is grown on the template top surface due to selectiveepitaxial growth, as there is a patterned dielectric (e.g., oxide and/ornitride) hard mask on top. Step 1958 (substrate release) corresponds tostep 1938 in FIG. 138. The hexagonal-prism 3-D TFSC substrate may thenbe used for subsequent 3-D TFSC fabrication. While FIGS. 138 and 139show the use of porous silicon sacrificial layers for fabrication ofdual-aperture TFSC substrates (without rear base layers), porous siliconcan also be used as a sacrificial layer for fabrication ofsingle-aperture TFSC substrates with rear base layers (using theappropriate template structure for single-aperture TFSC substrates, asdescribed before).

The preceding FIGURES outline process flow embodiments which result inhexagonal-prism 3-D TFSC substrates made of a crystalline(monocrystalline or multicrystalline) semiconductor material (preferablycrystalline silicon), through the use of conformal epitaxial depositiontechniques. In alternative embodiments, 3-D TFSC substrates are madefrom polycrystalline or amorphous semiconductor materials (such aspolysilicon or amorphous silicon). However, the resulting 3-D TFSCs mayexhibit lower efficiencies compared to the 3-D TFSCs made from acrystalline semiconductor (e.g., monocrystalline or multicrystallinesilicon).

FIGS. 140 and 141 depict embodiments of two process flows 1960 and 1980for fabrication of self-supporting hexagonal-prism 3-D dual-apertureTFSC substrates without rear base layers using layer release processingbut without the use of silicon epitaxy, unlike FIGS. 135 to 139 above.The template used in FIG. 140 has a patterned dielectric on the templatefrontside, while the template used in FIG. 141 has no dielectrics oneither the frontside or backside. The sacrificial layer used in theseprocess flows is simply a sacrificial dielectric layer such as SiO₂. Thesilicon material is amorphous silicon and/or polysilicon, which mayoptionally be subsequently crystallized using laser crystallization toform large-grain polysilicon or multicrystalline silicon (and thermallyannealed in order to reduce silicon film stress to facilitate releasefrom the template). These process flows result in 3-D dual-aperture TFSCsubstrates with hexagonal-prism unit cells with open apertures on bothtop and rear.

Referring to FIG. 140, step 1962 (providing a substrate) corresponds tostep 1952 from FIG. 139. Step 1964 involves depositing a conformalsacrificial layer (or a layer stack). First, a thin layer of asacrificial material is deposited by conformal layer formation (LPCVD orthermal oxidation). In one embodiment, the sacrificial material is SiO₂,with a thickness of between 50 and 2000 nanometers. This sacrificialoxide layer conformally covers the hexagonal-prism trench walls and thetemplate frontside. If subsequent laser crystallization is used (seestep 1972 below), step 1964 also includes depositing a thin nitridelayer by LPCVD. In one embodiment, this nitride layer is Si₃N₄, with athickness between 100 and 1000 nanometers. The sacrificial layer may bemade of porous silicon instead of oxide and/or nitride. Step 1966involves deposition of a blanket silicon layer using conformaldeposition. In one embodiment, this blanket silicon layer may beamorphous silicon or polysilicon, p-type in-situ doped with boron,having a thickness between 1 and 30 microns. Step 1968 uses selectivesilicon (wet or dry) etch to strip the top silicon layer, until the topsurface of sacrificial layer (e.g., silicon dioxide or silicon nitrideor porous silicon) is exposed. When using plasma (dry) etch process, oneembodiment uses optical end-pointing to ensure complete removal of topsilicon layer and exposure of the top porous silicon layer. If optionalnitride is used, the top Si₃N₄ layer is etched using selective wet ordry etch. Step 1970 involves 3-D TFSC substrate release. In oneembodiment and when using a silicon dioxide sacrificial layer,hydrofluoric acid (HF) is used to etch the oxide sacrificial layer. Inanother embodiment and when using a porous silicon sacrificial layer, amixture of ammonia, peroxide, and water (NH₄OH+H₂O₂+H₂O) or a mixture ofhydrogen peroxide and hydrofluoric acid (H₂O₂+HF) or a suitablecomposition of tri-methyl-ammonium-hydroxide (TMAH) may be used. Theetch composition and temperature may be adjusted to achieve maximum etchselectivity for porous silicon with respect to silicon. This processreleases the hexagonal-prism 3-D TFSC substrate. An optional step 1972involves laser crystallization and/or thermal annealing of the released3-D thin-film amorphous silicon or polysilicon substrate to form alarge-grain polysilicon microstructure (and to reduce any residualstress for the embedded silicon structure), where the nitride layerserves as protective cap. The nitride layer is then selectivelystripped. The hexagonal prism 3-D TFSC substrate may then be used forsubsequent 3-D TFSC fabrication.

Referring to FIG. 141, in step 1982, a patterned hexagonal-prismtemplate is provided. This template has already been processed to forman embedded array of deep interconnected trenches. In this case, thereare no dielectric hard mask layers on the template top and rearsurfaces. Step 1984 (conformal deposition of sacrificial layer)corresponds to step 1964 of FIG. 140; step 1986 (blanket silicondeposition) corresponds to step 1966; step 1988 (selective silicon etch)corresponds to step 1968; step 1990 (substrate release) corresponds tostep 1970; and step 1992 (optional laser crystallization) corresponds tostep 1972. The hexagonal-prism 3-D TFSC substrate may then be used forsubsequent 3-D TFSC fabrication.

While multiple embodiments are shown to depict various hexagonal-prism3-D TFSC substrate fabrication methods of this disclosure, theembodiments shown may be used to develop additional process flows andvariations based on the overall concepts, designs, embodiments, andmethodologies.

FIGS. 142 through 146 show Y-Y cross-sectional views of the evolution ofone prism unit cell of a template with through-wafer trenches 782, as itgoes through several key process steps for fabricating a hexagonal-prismdual-aperture 3-D TFSC substrate without a rear base layer. The processflow outlined in these FIGURES includes the use of both blanket andselective epitaxial growth based on the relevant process flowembodiments described earlier. While shown with a dielectric stack onthe template frontside and backside, the process flow using blanketepitaxial deposition may proceed without using the dielectric stack onthe template frontside.

FIG. 142 shows a Y-Y cross-sectional view 2000 of a template withthrough-wafer trenches 782 after deposition of a thin sacrificial layer(epitaxial Ge_(x)Si_(1-x) or porous silicon) 1138 followed by depositionof a blanket in-situ-doped (e.g., boron-doped for p-type base) epitaxialsilicon layer 1140. The dielectric top hard mask layer is composed of afirst top hard mask layer 2002 of Si₃N₄ on top of a second top hard masklayer 2004 of SiO₂ on top of the template top surface 2006. Thesacrificial layer 1138 forms a thin layer on both the sidewalls 144 andon the template top surface 2006 (being formed on the top surface of thefrontside dielectric 2002). This sacrificial layer 1138 forms a thinlayer (e.g., 100 to 2000 nanometers thick) between the in-situ-doped(boron-doped) epitaxial silicon 1140 and the template.

FIG. 143 shows a view 2010 after a controlled silicon etch to remove thep-type silicon epitaxial layer 1140 from the top of the template only(leaving epitaxial silicon in trenches). FIG. 144 shows a template view2020 after a highly selective wet etch process to remove the sacrificiallayer 1138 (Ge_(x)Si_(1-x) or porous silicon or another suitable layer)shown in FIG. 143. Removal of the sacrificial layer 1138 results in theformation of a gap 1152 between the template and the p-type siliconepitaxial layer (i.e., the 3-D TFSC substrate) 1140, allowing forrelease and removal of the 3-D TFSC substrate from the template. Releaseof the substrate 1140 may be facilitated by ultrasonic agitation and/ormagnetically coupled etchant stirring during selective wet etching ofthe sacrificial layer 1138. FIG. 145 shows a view 2030 of the templateafter lifting off the p-type silicon epitaxial layer 1140. The template780 (see FIG. 39) is ready for multiple reuse cycles.

FIG. 146 shows three cross-sectional views. View 2040 shows a larger Y-Ycross-sectional view of the template shown in FIG. 145, with multipleprism unit cells shown. View 2042 shows a Y-Y cross-sectional view ofthe hexagonal-prism 3-D TFSC substrate 1140 after release from thetemplate shown in view 2040 (with the emitter side down). Note that thebase and emitter sides are shown on the top and rear, respectively. View2044 shows a Y-Y cross-sectional view of the hexagonal-prism 3-D TFSCsubstrate 1140 (vertically flipped view compared to view 2042) afterrelease from the template shown in view 2040. Note that the emitter andbase sides are shown on the top and rear, respectively.

FIGS. 147 through 150 show Y-Y cross-sectional views of the evolution ofone prism unit cell within a template with in-wafer trenches 802 and nodielectric layers on the template frontside or template backside, as itgoes through several key process steps for fabricating a hexagonal-prismdual-aperture 3-D TFSC substrate without a rear base layer. The processflow outlined in these FIGURES includes the use of both blanket andselective epitaxial growth based on the relevant process flowembodiments described earlier.

FIG. 147 shows a Y-Y cross-sectional view 2050 of a version of thetemplate 880 (see FIG. 48) with in-wafer trenches 802 without adielectric top mask layer or a dielectric rear mask layer. The deeptrenches may be formed using lithography patterning and deep RIE (DRIE).FIG. 148 shows a view 2060 after deposition of the relatively thin(e.g., 200 to 2000 nanometers) sacrificial layer 1138 (epitaxialGe_(x)Si_(1-x) or porous silicon or another suitable material) and thein-situ-doped (boron doped for p-type base or phosphorus doped forn-type base) epitaxial silicon layer 1140 to fill the hexagonal-prismtrenches. FIG. 149 shows a view 2070 after controlled plasma or wetetching of the in-situ-doped (boron-doped for p-type base) epitaxialsilicon layer 1140 on the template frontside, endpointing or stoppingthe etch on the top of or within the frontside sacrificial layer 1138.FIG. 150 shows a view 2080 after highly selective wet etching ofsacrificial layer 1138 (epitaxial Ge_(x)Si_(1-x) or porous silicon) torelease the hexagonal-prism 3-D TFSC substrate 1140. The dual-aperture3-D TFSC substrate with embedded silicon sidewalls is ready to bedetached and removed from the template.

FIGS. 151 through 154 illustrate Y-Y cross-sectional views of a template900 (see FIG. 50) with through-wafer trenches 782 and a backside layer794 (trenches penetrating through the template bulk and terminated onthe supporting backside dielectric layer 794) and no dielectrics on thetemplate frontside, as it goes through the key process steps tofabricate a hexagonal-prism dual-aperture 3-D TFSC substrate without arear base layer. Again, the flow used for this fabrication process flowis based on one of the embodiments outlined earlier.

FIG. 151 shows a Y-Y cross-sectional view 2090 of a version of thetemplate 900 with through-wafer trenches 782 without a top hard masklayer, but with a backside mechanical support layer 794. FIG. 152 showsa view 2100 after formation or deposition of the relatively thinsacrificial layer 1138 (epitaxial Ge_(x)Si_(1-x) or porous silicon oranother suitable material) and the in-situ-doped (boron-doped epitaxialfor p-type base) epitaxial silicon layer 1140. FIG. 153 shows a view2110 after controlled plasma or wet etching of the epitaxial siliconlayer 1140 on the template frontside, endpointing or stopping the etchon the top of or within the frontside sacrificial layer 1138. FIG. 154shows a view 2120 after selective wet etching of the sacrificial layer1138 (epitaxial Ge_(x)Si_(1-x) or porous silicon) to release thehexagonal-prism 3-D TFSC substrate 1140. The dual-aperture 3-D TFSCsubstrate with embedded silicon sidewalls is ready to be detached andremoved from the template.

FIG. 155 shows a view 2200 of a single unit cell 106 from thehexagonal-prism 3-D TFSC substrate for reference with calculations ofthe unit cell prism sidewall area, hexagonal-prism unit cell aperturearea, and the sidewall to planar base area ratio. These calculations areperformed for both types of single-aperture and dual-aperturehexagonal-prism 3-D TFSC substrates, both with and without rear baselayers. The long diagonal dimension of the unit cell hexagon (d) 164 maybe chosen in the range of roughly 50 microns to roughly 500 microns,with more typical values in the range of 100 to 250 microns. Thehexagonal-prism aspect ratio (H/d or height 172 to long hexagonaldiagonal dimension 164 ratio) may be anywhere between roughly 0.5 and 5,with more typical values between 1 and 3. The silicon film thickness W108 may be in the range of roughly 1 to 30 microns, with typical valuesin the range of 2 to 10 microns. Point A 2202 is the mid-point betweenH₅ 160 and H₆ 162. Point B 2204 is the mid-point between H₂ 154 and H₃156.

Short hexagonal diagonal distance between opposite unit cell points 2202and 2204 (h)

h=(√3/2)d=0.866d

Planar surface Area of hexagonal-prism 3-D TFSC substrate hexagonal top(or rear) base (S_(hb))

S _(hb)=[(3√3)/8]·d ²

Surface Area of hexagonal-prism unit cell cavity walls (fordual-aperture cell without rear flat silicon layer) (S_(hp))

S _(hp)=3·d·H

Surface Area of hexagonal-prism unit cell cavity walls (for cell withrear flat silicon layer) (S_(hp))

S _(hp)=3·d·H+[(3√3)/8]·d ²

For dual-aperture hexagonal-prism TFSC substrate without rear flatsilicon layer:

S _(hp) /S _(hb)=[8/√3]·(H/d)

For single-aperture hexagonal-prism TFSC substrate with rear flatsilicon layer:

S _(hp) /S _(hb)=[8/√3]·(H/d)+1

For the following calculations, assume W is the hexagonal prism sidewallsilicon film thickness. Also assume that W/2 is the prism base siliconthickness for hexagonal-prism TFSC substrate with rear flat siliconlayer:

Volume of silicon per prism unit cell for dual-aperture hexagonal-prismwithout rear flat silicon layer is:

V _(hp)=3·d·H·(W/2)=(3/2)d·H·W

Volume of silicon per prism unit cell for single-aperturehexagonal-prism with rear flat silicon layer is:

V _(hp)=(3/2)d·H·W+[(3√3)/8]·d ²(W/2)

The ratio of silicon volume V_(hp)/V_(F) (or mass M_(hp)/M_(F)) for thehexagonal-prism 3-D TFSC substrate with prism sidewall thickness of W tovolume (or mass) for a flat silicon wafer or film with the waferthickness W_(F) is as follows (shown for dual-aperture honeycomb-prismTFSC substrate without rear flat silicon layer):

V _(hp) /V _(F) =M _(hp) /M _(F)=(4/√3)[(H/d)·(W/W _(F))]

The ratio for the single-aperture honeycomb-prism TFSC substrate withthe rear flat silicon layer is as follows:

V _(hp) /V _(F) =M _(hp) /M _(F)=(4/√3)[(H/d)·(W/W _(F))]+[W/(2·W _(F))]

FIGS. 156 and 157 help to illustrate the important results of the abovecalculations. FIG. 156 shows a graph of hexagonal-prism area ratio, forTFSC substrates with and without rear base layers. The Y-axis is theratio of hexagonal-prism unit cell aperture area to hexagonal-prism unitcell base area. The X-axis is the ratio of hexagonal-prism unit cellheight to unit cell base diagonal dimension (H/d or unit cell aspectratio). FIG. 157 shows a graph of hexagonal-prism mass ratio, for 3-DTFSC substrates with and without rear base layers. The Y-axis is theratio of honeycomb-prism substrate silicon mass to the mass of a flatsilicon wafer. The X-axis is the ratio of honeycomb prism sidewallthickness to the thickness of a flat silicon wafer.

FIGS. 156 and 157 show that the hexagonal-prism 3-D TFSC substrates maybe designed such that they have much larger solar absorption surfacearea (in conjunction with a 3-D structure facilitating lightcapture/trapping) while consuming much less silicon volume (and hencemuch less silicon mass) compared to standard flat silicon wafers.

For a hexagonal-prism TFSC substrate without a rear flat layer, thetotal unit cell absorber silicon volume (or mass) is half the volume (ormass) of the unit cell prism sidewalls. This is because only half of thesidewall volume or mass belongs to each unit cell. For a hexagonal-prismTFSC substrate with a rear flat layer, the total unit cell absorbervolume (or mass) includes the sum of half the volume (or mass) of theunit cell prism sidewalls and the volume (or mass) of the rear baselayer.

As indicated, the 3-D thin-film hexagonal-prism TFSC substrate designsof this disclosure have substantially smaller silicon volume (or mass)compared to the current state-of-the-art solar cell silicon wafers,which typically use wafers with thicknesses of more than 200 microns.This is particularly true for designs with unit cell aspect ratios (H/d)of less than 3. For a given thin silicon film thickness and substratesize, the amount of silicon material used (as measured by the totalsilicon surface area, volume, or mass) in the hexagonal prism 3-D TFSCsubstrate is larger than that of a co-planar (flat) substrate with thesame dimensions. However, the amount of silicon used is considerablyless than the amount of silicon used in standard crystalline silicon(c-Si) wafer solar cells. The hexagonal-prism 3-D TFSCs of the currentdisclosure consume 3 times to over 10 times less silicon than standardc-Si wafer solar cells.

To achieve efficient light capture/trapping within the 3-D thin-filmhexagonal-prism cell structure and very low effective surfacereflectance with a reasonable (i.e., not excessive) area enlargementfactor of S_(hp)/S_(hb), the prism aspect ratio H/d may be in the rangeof 1 to 3.

One of the major advantages of the hexagonal prism 3-D TFSCs of thisdisclosure is negligible shadowing (optical reflectance loss) effects ofthe emitter and base contact metallization. Essentially any reflectionsfrom the base hexagonal contact metal may be received by the hexagonalprism silicon absorber and may contribute to the photogenerated current.Also, the combination of the thin prism sidewall on the top emitter sidein conjunction with the rounding of the top hexagonal ridges beforeemitter contact metallization and the unit folded structure of theemitter contact metallization may ensure that most of the sunlightreflections would be redirected into the prism cavity sidewalls and/orthe hexagonal prism cavity base layer (the rear base silicon layer inthe case of cells with rear base layers and also the rear mirror, in thecase of all hexagonal prism cell designs with and without rear baselayers). A small fraction of the sunlight incident on the top of thereflective emitter contact may escape the hexagonal prism cellcavity/aperture. This may be further minimized by coating the cell withan additional layer of mechanical protection and ARC layer duringglassless module assembly. As an example, FIG. 158 shows a schematicdiagram 2210 of ray tracing for solar rays 2212 incident on a hexagonalprism unit cell reflective emitter contact. As indicated here, most ofthe sunlight rays (including incident rays R₁ 2214, R₂ 2216, R₃ 2218, R₄2220, R₅ 2222) incident on the folded emitter contact are reflected back(shown as reflected rays R₁ 2215, R₂ 2217, R₃ 2219, R₄ 2221, R₅ 2223,with R₁ 2215 being the lone exception) into the prism unit cell cavity2224 and/or onto the rear mirror 2226 (or the rear base layer in thecase of cells with rear base layers) and ultimately contribute to theTFSC electricity generation (due to the folded emitter contact metaldesign on the hexagonal prism top ridges). The prism sidewall and theemitter contact metal on the top may be optimally tapered in order tominimize any shadowing losses due to the emitter contact metal.Moreover, a protective transparent coating layer formed over the cellduring the final solar module assembly (e.g., a proper coating layerformed by liquid spraying and curing over the cell) may further reducethe reflection losses associated with the top emitter contact metal.Optical waveguiding of the rays incident on the top of the emittercontact metal redirects the incident rays from the top of the emittercontact metal into the hexagonal-prism unit cell cavity 2224.

FIG. 159 shows ten rays 2212 incident on a hexagonal-prism unit cell ata normal angle of incidence for the purpose of ray tracing calculations.FIG. 160 shows ten rays 2212 at an angle of incidence of 45 degrees forthe purpose of ray tracing calculations. FIG. 161 shows three rays 2212at a normal angle of incidence for the purpose of ray tracingcalculations. FIG. 162 shows three rays 2212 at an angle of incidence of45 degrees for the purpose of ray tracing calculations.

FIG. 163 shows a summary graph of short circuit current density versusangle of incidence for several embodiments of the solar cells of thecurrent disclosure. FIG. 163 also shows the ray tracing results for ahexagonal-prism unit cell with a base layer, indicating super-efficientlight trapping. FIG. 164 shows a summary graph of the basic ray tracingmodeling results for a single-aperture hexagonal-prism cell design ofthis disclosure, indicating both the STC cell efficiency andshort-circuit current versus unit cell prism height. Note thatultra-high-efficiency (greater than 25% STC efficiency) capability ofthe cell designs of this invention has been verified through modeling.FIG. 165 shows a summary graph of the results of ray tracing modelingresults in a single-aperture hexagonal-prism cell design of thisinvention (with a base layer), with maximum photocurrent plotted againstincident angle. This FIGURE indicates that the emitter wrap-aroundmetallization actually increases the photogenerated current density as aresult of improved light trapping within the prism sidewalls.

Throughout descriptions of various embodiments of this disclosure, ithas been stated that the hexagonal-prism 3-D TFSC substrate may be dopedin-situ during semiconductor layer deposition (e.g., epitaxial silicongrowth) onto the reusable templates. The hexagonal-prism 3-D TFSCsubstrate base doping may be uniform or graded. In case of optimalgrading of the hexagonal prism 3-D TFSC substrate doping, the substratemay provide an internal electric field due to the graded substratedoping which may facilitate or aid photogenerated carrier collection dueto a field-assisted carrier drift component. Dopant concentrationgrading may be done linearly, logarithmically, or in another suitablescaling method. As an example, FIG. 166 shows a graph of the selectiveemitter phosphorus and 3-D substrate boron doping profiles (prismsidewall-to-sidewall doping profile) in hexagonal prism 3-D TFSCs ofthis disclosure, indicating a representative graded base doping profile.As indicated before, the graded base doping profile helps withphotogenerated carrier collection efficiency and a reduction of the baseparasitic resistance (and the resulting ohmic losses), thus, improvingthe short circuit current and fill factor of the cells. This example isshown for a boron-doped base and phosphorus-doped emitter. In the caseof hexagonal-prism cells with rear base layers, the graded base dopingalso creates a graded boron doping profile with the boron concentrationbeing lower on the top surface (emitter side) of the rear base layer andincreasing towards the lower surface (base side) of the rear base layer.This provides a desirable back-surface field (BSF) effect which improvesthe carrier collection efficiency in the rear base layer as well andreduces the surface recombination velocity in the rear base layer.

In order to maximize the hexagonal-prism 3-D TFSC efficiency, it isimportant to design the cell such that the ohmic losses associated withthe electron and hole currents within the cell structure are minimized.This is in addition to the need to make the emitter and baseinterconnect metallization ohmic losses negligible. Assuming aboron-doped base and an n⁺ selective emitter, the ohmic losses withinthe hexagonal-prism cell structure are dominated by theemitter-collected electrons traveling along the selective emitter regiontowards the emitter contact metal on the prism top (or the emittercurrent traveling from the emitter contact metal towards the selectiveemitter) as well as the base-collected holes (or the base current)traveling along the hexagonal prism boron-doped sidewall bulk towardsthe base contact metal at the rear of the cell (the above-mentionedcarrier polarities would be inverted for phosphorus-doped n-type baseand p⁺ selective emitter).

Referring to FIG. 167, the following section outlines the summarycalculation of the hexagonal prism TFSC ohmic losses due to the basecurrent along the prism sidewalls. These calculations assume that allphotogenerated current is in the prism sidewalls (and assume that thephotogenerated current is negligible in the rear base layer in the cellswith rear base layers). The results should be fairly similar to thoseobtained even after taking into account the photogenerated current dueto the rear base layer for the cells with rear base layers. It is alsoassumed that the photogenerated current contribution is uniform alongthe height of the prism sidewall (i.e., each fixed small verticalsegment of the prism sidewall contributes equally to the photogeneratedcurrent. Thus, the base ohmic losses may be estimated through a simpleintegration of the differential ohmic losses along the prism sidewallfrom rear to top of the prism (or from top to rear of the prism) as thephotogenerated current increases from 0 to the maximum hexagonal-prismunit cell current. For the base ohmic losses to be negligible (less than0.1% or 1/1000 of the maximum cell power, assuming 200 W/m² maximum cellpower generation), it is determined that the prism sidewall base sheetresistance should be less than roughly 300 Ω/square. This determines theminimum base boron doping concentration. In practice, the sheetresistance is chosen to be roughly 300 Ω/square and not much below thatin order to prevent lowering of the minority carrier lifetime as aresult of excessive base doping concentration. Minority carrierlifetimes in the range of more than 10 to more than 100 microseconds, orminority carrier diffusion length L_(eff) on the order of a multiple(e.g., by a factor of more than 2 to 5) of the hexagonal prism sidewallthickness should meet the high-efficiency requirements for the cells.

To calculate base ohmic losses, assume all base current is produced inthe prism sidewall. The photo-generated base current is assumed toincrease linearly between z=0 and z=H from 0 to I₀ (where I₀ is thephoto-generated current per prism unit cell). The base current iscollected at the base contact metal at z=H (at the rear of the honeycombprism base layer). The base ohmic loss per unit cell (P_(uc)) iscalculated as follows (R_(sb) is the prism sidewall base sheetresistance; I₀=J₀ S_(hb), where J₀ is the solar cell maximum-powercurrent density and S_(hb) is the surface area of the prism hexagonalaperture).

$P_{uc} = {{\int_{0}^{H}{\frac{2R_{sb}{z}}{3d}( \frac{I_{0}z}{H} )^{2}}} = {{\frac{2R_{sb}I_{0}^{2}}{9}( \frac{H}{d} )} = {\frac{2R_{sb}J_{0}^{2}S_{hb}^{2}}{9}( \frac{H}{d} )}}}$

The base ohmic loss per unit area (P_(bl)) is calculated by dividing Pucby the hexagonal aperture area:

$P_{bl} = {{P_{uc}/S_{hb}} = {{\frac{2R_{sb}J_{0}^{2}S_{hb}}{9}( \frac{H}{d} )} = {\frac{2R_{sb}J_{0}^{2}}{9}{{( \frac{H}{d} )\lbrack {3{\sqrt{3}/8}} \rbrack} \cdot d^{2}}}}}$$P_{bl} = \frac{\sqrt{3}R_{sb}J_{0}^{2}{dH}}{12}$

Assume d=100 microns, H=300 microns and J₀=40 mA/cm²:

P _(bl)=(√3/12)R _(sb)(40×10⁻³×10⁴)(100×10⁻⁶)(300×10⁻⁶)

P _(bl)=6.93×10⁻⁴ R _(sb) (units are in W/m²)

Assume P_(bl) is much less than 200 W/m²; for instance, assume: P_(bl)=(1/1000)200=0.2 W/m²:

P _(bl)=0.2=6.93×10⁻⁴ R _(sb) →R _(sb)=288.6 Ω/square

Thus, R_(sb) should be less than 300 Ω/square in order for the baseohmic losses to be negligible.

The selective emitter sheet resistance is typically in the range ofroughly 75 Ω/square up to roughly 150 Ω/square. Thus, the ohmic lossesassociated with the selective emitter current are expected to be lessthan the ohmic losses due to the base current (for base sheet resistancevalues on the order of 300 Ω/square as shown above. In summary, we mayconclude that for optimal hexagonal prism 3-D TFSCs of this disclosure,both with and without rear base layers, the overall internal (within Si)ohmic losses due to the base and emitter current components may be madenegligible (or roughly 0.1% of the photogenerated cell power or less),when the cells use prism sidewall layers (and rear base layers in thecase of cells with such rear base layers) which have sufficient basedoping to produce a sheet resistance of roughly 300 Ω/square (or less),and have selective emitter with a sheet resistance value of less than150 Ω/square. Of course, these sheet resistance values may still beincreased while maintaining the internal ohmic losses to much less than1% of the photogenerated cell power.

The hexagonal prism 3-D TFSC maximum base sheet resistance valuecalculated above may be used in conjunction with the silicon thicknessforming the hexagonal prism sidewalls in order to determine the optimal(or near-optimal) base resistivity and doping concentration.

Assuming a boron-doped p-type base, FIG. 168 shows the approximatedesired base boron doping concentration and electrical resistivityvalues for different values of hexagonal prism 3-D silicon filmthickness in the range of 2 to 30 microns in order to keep the baseohmic losses to below 0.1% of the TFSC power. These values were obtainedbased on the calculations outlined above. The same methodology may beapplied to optimizing the cell doping concentrations and profiles forcells using other absorber materials other than c-Si (such aspolysilicon, amorphous silicon, or a non-Si semiconductor material).Moreover, while these calculations are shown for determining theapproximate optimal doping concentrations for uniformly doped baseregions, they may also serve as guides for determining the desiredin-situ-doped graded base profiles.

Assume P_(bl) is much less than 200 W/m²; e.g., assume: P_(bl)=(1/1000)200=0.2 W/m²:

P _(bl)=0.2=6.93×10⁻⁴ R _(sb) →R _(sb)=288.6 Ω/square

Thus, R_(sb) should be less than 300 Ω/square in order for the baseohmic losses to be negligible.

R _(sb) ≈ρ/W→ρ≈R _(sb) ×W, where W is the silicon thickness.

For R_(sb)≈300 Ω/square, the maximum base resistivity values for variousprism silicon thicknesses are shown in FIG. 168. Note that the resultsare shown for a hexagonal-prism substrate with d of 100 microns and H of300 microns. Selective emitter sheet resistance is chosen to be on theorder of 100 Ω/square to 150 Ω/square; therefore, the emitter currentohmic losses are less than the base current ohmic losses and areexpected to be much less than 0.1% of the maximum cell power generation.

The hexagonal-prism 3-D TFSC substrates of this disclosure may utilizeperipheral thick silicon frames, both for added mechanical support andalso to facilitate formation of wrap-through or wrap-around emittercontact metallization (for ease of solar module assembly). FIGS. 119Aand 119B show the Y-Y cross-sectional views of a hexagonal-prism 3-DTFSC substrate using a thick silicon frame, before and after TFSCfabrication (relative substrate dimensions not shown to scale since inpractice the a large substrate such as a 200 mm×200 mm substrate hasthousands to millions of prism unit cells). The thick silicon frame maybe separately made from very low-cost silicon material (such asmetallurgical grade or reclaim silicon wafers). FIG. 169 shows variousschematic views 2230 of the thick silicon frame, the silicon frameslivers, and representative method to produce (e.g., cut) siliconslivers from very-low-cost round (e.g., reject silicon frommicroelectronics) or square-shaped (or rectangular) cast silicon (orreclaim Si) substrates. The slivers may be made of very low-costcrystalline or multicrystalline silicon such as metallurgical-grade castSi. A round 2232 or square-shaped 2234 silicon wafer (e.g., a 200 mm×200mm cast metallurgical-grade silicon substrate) may be used to producehundreds of silicon slivers 2236 by a cutting process such as lasercutting (four slivers used to make a thick silicon frame for a 3-D TFSCsubstrate by a welding process such as electron-beam welding).

These slivers 2236 may be used to make the thick silicon frames for thesubstrates shown in FIGS. 119A and 119B. The separately fabricated thicksilicon frame may then be integrally attached to the hexagonal-prism 3-DTFSC substrates, in embodiment before 3-D thin-film cell processing, byone of the following techniques: electron-beam welding at severalperipheral spots/junctions; attachment during the hexagonal prism 3-DTFSC substrate fabrication silicon deposition by placing the peripheralthick silicon frame on the template and allowing seamless attachment ofthe thick silicon frame to the 3-D TFSC substrate by the silicondeposition process; or a clean cured epoxy.

Top view 2240 shows a thick silicon frame to be fused to the 3-D TFSCsubstrate. The silicon frame thickness 2242 is roughly 50 to 500microns. There are welded (e.g., e-beam-welded) joints 2244 (four weldedjoints), where L 2246 is roughly 150 to 300 millimeters, and where W2248 is roughly 100 to 1000 microns. The slivers 2236 may also havethrough-holes (shown in view 2250) to help with thewrap-through/wrap-around emitter metallization contacts.

The main sources of efficiency drop from the cell-level efficiency tothe module-level efficiency (efficiency gap between the cells andmodules) in the state-of-the-art prior art commercial solar cells andmodules are: ohmic power losses due to the cell electrical contacts andinterconnects; ohmic power losses due to the cell-to-module electricalinterconnects as well as the module cell-to-cell electricalinterconnects (connecting the cells in series and/or in combinationseries/parallel); ratio of total active front cell area to the totalmodule front area (area cells-to-module area ratio); and frontside glasscover reflectance (and transmittance) losses. The combination of theselosses may cause a cell-to-module efficiency drop or gap of at leastroughly 4% to 7% in the state-of-the-art prior art solar modules. Thesolar cell and module assembly designs of this disclosure enable asubstantial reduction of this cell-to-module efficiency gap to belowroughly 1% to 3%. This is accomplished by: high ratio of active cellarea to module area (more than 99%); much reduced ohmic power losses dueto the cell and module electrical contact/interconnects (to well below1% to 2% due to the unique cell and module contact and interconnectdesigns and the printed-circuit board assembly features); andsubstantially reduced frontside cover optical reflectance/transmittancelosses due to glassless module passivation or textured-glass-coveredmodule designs (optical reflectance/transmittance losses reduced to lessthan 1%).

In the next section, various embodiments of this disclosure for makingsolar modules suitable for building rooftops and façades, centralizedpower generation, and other applications are described. Usually solarmodules are made by arranging a plurality of solar cells and connectingthem in series (series electrical connections) within a solar moduleassembly protected by a top glass layer and a rear protective materiallayer such as Tedlar. The cells may be connected in series in order tostep up the DC voltage (while maintaining the solar module current atthe same level at the level of the cell current) to facilitatehigh-efficiency DC-to-AC power conversion.

FIG. 170 shows a view 2260 of a representative example of seriesconnections of TFSCs of this disclosure in a solar module assembly. Thisexample shows 24 squared-shaped cells 2262 connected in series (in a 6×4array). The electrical connections in series are shown by arrows betweenthe adjacent cells connected in series. Module power input and outputleads 2264 are also shown. In actual module assemblies, the numbers ofcells may be smaller or larger and the cells may be connected in seriesor in a combination of series and parallel. As mentioned earlier, seriesconnection of the cells within the module assembly allows for steppingup the DC voltage for the DC-to-AC inverter (and also limiting the DCcurrent of the solar modules for ease of module installation in thefield and reliability of the module-to-module electrical connections).The printed-circuit-board (PCB) based module assembly of this disclosuresupports any number of cells assembled in a module and any electricalconnection configuration (series, series/parallel combination, orparallel). The TFSCs and modules of this disclosure may providerelatively lightweight solar modules with areas from less than 1 m² toseveral m² (e.g., 10 m²) for various applications. The cells connectedin series within a module assembly are chosen based on sorting to bematched in terms of their photogenerated current (e.g., short-circuitcurrent I_(sc) and/or maximum-power current I_(m)).

The solar module structures and assembly methods of this disclosure arebased on the use of a printed-circuit board (PCB) to assemble thehexagonal prism 3-D TFSCs in a closely packed array and to connect thecells (in one embodiment in series) using the PCB plate within a moduleassembly. The PCB plate may have a single patterned metal (in oneembodiment, copper) interconnect layer on the top of the PCB or twopatterned copper layers on the top and rear surfaces of the PCB plate.FIG. 171 shows a view 2270 of the frontside silver-coated copper layoutof the printed-circuit board (PCB) used for solar module assembly (thesquare islands serve both as rear mirrors (if no integrated mirror isused with single-aperture cells, or if the cells are dual-aperture cellswithout base layers) and base interconnects; the peripheralsquare-shaped copper bands connect to the wrap-around emitter contact atthe TFSC peripheral frame rear side; copper-filled via plugs connectingselect regions of the PCB frontside and backside are shown as smallcircles). This example is shown for an array of 24 TFSCs arranged in 4rows of 6 cells in each row (the PCB may be designed for any number andvarious arrangements of TFSCs). The PCB conductor (copper or aluminum)thickness may be in the range of roughly 10 to over 100 microns toprovide high electrical and thermal conductivities. The PCB also servesas an effective heat sink to minimize temperature cycling of the TFSCsin operation. The PCB material may be selected to be a lightweight,high-strength material (such as carbon composite materials used inaerospace industry), or even a relatively thin flexible material. Thelarger-area square-shaped silver-coated copper regions 2272 areconnected to the TFSC rear base regions (bottoms of the rear base layersfor the single-aperture cells or the bottom ridges of the dual-aperturecells for the dual-aperture cells). The peripheral silver-coated copperlines 2274 are electrically connected to the TFSC emitter contactmetallization regions.

FIG. 172 shows a top view 2280 of the backside (optionallysilver-coated) copper layout of the printed-circuit board (PCB) used forsolar module assembly, showing the series connection of the TFSCs. ThePCB backside may also include thin-film shunt diodes for shadeprotection of the TFSCs (as shown in FIG. 171). The copper-filled viaplugs (shown as circles) connect the PCB frontside and backsidemetallization patterns in the corresponding areas. While the exampleshown here is for connecting 24 TFSCs in series on a solar panel,similar PCB design methodology may be applied to configure and connectany number of cells in any desired arrangements on the module. Thefrontside view of this PCB is shown in FIG. 171. This example is shownfor an array of 24 TFSCs arranged in 4 rows of 6 cells in each row (thePCB may be designed for any number and various arrangements of TFSCs),all connected in series. The PCB conductor (copper or aluminum)thickness may be in the range of roughly 10 to over 100 microns toprovide high electrical and thermal conductivities. The PCB also servesas an effective heat sink to minimize temperature cycling of the TFSCsin operation. The PCB material may be selected to be a lightweight,high-strength material (such as suitable carbon composite materials usedin aerospace industry). FIG. 172 also shows power Output Lead 2282(first cell's p-lead) and power output lead 2284 (last cell's n-lead).

FIG. 173 shows a backside view 2290 of the copper pattern on the PCB andis essentially similar to FIG. 172. This picture also shows the use ofprotective thin-film shunt diodes mounted on the PCB backside pattern(for cell shadow protection).

FIG. 174A shows an enlarged top view 2300 of the silver-coated copperpattern (the pad for mounting one cell) on the frontside of the solarmodule printed-circuit board (PCB) used for rear mirror and also emitterand base interconnects for one of the TFSCs (relative dimensions are notshown to scale). FIG. 174A shows dimensions of L₁ 2302 and L₂ 2304 (inone embodiment, 150 millimeters to greater than 200 millimeters, whereL₂=L₁+2(W+S)). S 2306 may be on the order of 25 to 250 microns. Thewidth of the peripheral copper conductor band (W) 2308 may be on theorder of 50 to 500 microns. The copper-filled via plugs 428 are shown ascircles (connecting the interconnect patterns on the PCB frontside andbackside in a pre-designed arrangement in order to connect the TFSCs inseries or in any other desired arrangement such as series/parallel; therepresentative example shown here is for connecting all the cells inseries in order to step up the module open-circuit voltage). The viaplug 428 diameters may be on the order of roughly 50 to 500 microns (andmay be smaller than W 2308). The large central square pad serves both asthe rear cell mirror (for dual-aperture cells or single-aperture cellswithout integrated rear mirrors) and also base interconnect plane(connecting to the hexagonal-prism base contact metallization). Thenumber of vias in the center square (p-region contact) (N) 2310 may beon the order of hundreds to thousands. The number of vias in theperipheral line (n-region contact) (M) 2312 may be on the order of tensto hundreds (or even thousands). The vias on the peripheral linecontacting the TFSC emitter (n) regions are placed on three sides. ThePCB conductor (copper or aluminum) thickness may be in the range ofroughly 10 to over 100 microns to provide high electrical and thermalconductivities. The PCB plate also serves as an effective heat sink tominimize temperature cycling of the TFSCs in field operation. ThisFIGURE shows one of the copper interconnect/mirror pads shown in thefull module PCB array of FIG. 171.

FIG. 174B shows an enlarged top view 2320 of the silver-coated copperinterconnect pattern on the backside of the solar module printed-circuitboard (PCB) used for emitter and base electrical interconnects for acouple of adjacent TFSCs of this disclosure (a portion of the PCB view).FIG. 174B shows the PCB backside silver-coated copper interconnectpattern for TFSCs 1 and 2 in the array. The copper pattern here is shownfor connecting the TFSCs in series to step up the module open-circuitvoltage. FIG. 174B shows dimensions of L₁′ 2322; peripheral emitter(n-region) connector linewidth W′ 2324 (in one embodiment, 2 to 10millimeters); spacing between the center base (p-region) connector plateand the peripheral emitter (n-region) connector line S′ 2326 (in oneembodiment, 100 microns to 1 millimeter). Note that L₁′ 2322 is lessthan L₁ from FIG. 174A by roughly 2 to 10 millimeters. This enableslarger peripheral emitter (n-region) connector linewidth andsubstantially reduced ohmic losses on the PCB backside.

The PCB assembly described above may be used to create the final solarmodule assembly in a number of ways (with or without a frame, with orwithout top tempered glass, etc.).

FIG. 175 shows a cross-sectional view 2330 of a solar module (solarpanel) structure with a protective back plate 2332 made of a provenprior art material (e.g., Tedlar or polyvinyl fluoride film); a rearencapsulant layer 2334 (EVA), a 2-sided printed-circuit board (PCB) 2336of this disclosure with rear patterned electrical interconnects 2338 andtop patterned electrical interconnects 2340; cell rear mirrors (ifapplicable for instance, for single-aperture cells with integrated rearmirrors) and TFSCs 2342 with rear base and wrap-around (or wrap-through)emitter contacts mounted on the frontside of the PCB, a top encapsulatelayer (EVA) 2344, and an anti-reflection-coated (ARC) tempered glass (inone embodiment, textured tempered glass) 2346 (from rear to top), withgreater than 98% transmission, with sputtered or sprayed orliquid-coated anti-reflection coating). This module structure may beassembled as a hermetically sealed package either as a frameless moduleor with a frame (e.g., made of aluminum). In one embodiment, the moduleassembly is a frameless assembly (also for reduced materials energycontent and reduced energy payback time).

FIG. 176 illustrates a first embodiment of a process flow 2350 forfabrication of solar modules with top protective glass plates andembedded PCBs of this disclosure (corresponding to the solar modulestructure of FIG. 175 with a PCB and a TFSC mounted on the PCB). Thismanufacturing flow is compatible with a fully automated module assemblyline. This module assembly flow is based on the use of a double-sidedprinted-circuit board (PCB) with the cell rear mirrors/baseinterconnects on the PCB topside (silver-coated patterned copper on thePCB topside). For hexagonal-prism 3-D TFSCs with rear base layers andintegrated/embedded (or attached) rear mirrors fabricated prior tomodule assembly (e.g., hexagonal-prism cells with rear base layers andthin-film rear mirrors deposited on the rear surfaces of the rear baselayers using PVD or plating or roller coating/spray coating and curing),the patterned PCB copper layer does not have to be coated with ahigh-reflectivity mirror material (silver). In step 2352, moduleassembly starts with a double-sided PCB coated with copper foils on bothfrontside and backside. The PCB area should support the desirednumber/layout of TFSCs (e.g., ≧1 m², with a copper foil thickness oneach side of roughly 10 to over 100 microns). Step 2354 involves PCBinterconnect patterning and silver flash coating (the latter if neededfor PCB rear mirror). The PCB frontside and backside copper foils arepatterned according to the desired frontside and backside interconnectlayouts. Copper patterns are flash coated with a thin layer of highlyreflective silver (and/or aluminum). A highly reflective diffuse mirrormay be used, though a specular mirror may also be used. Step 2356involves cell preparation for automated TFSC placement and soldering.The rear hexagonal metallized side of the TFSCs is roller coated (orspray coated or dip coated) with lead-free solder or an electricallyconductive and thermally-conductive epoxy paste. For cells fabricatedusing a honeycomb-prism TFSC substrate without a rear flat silicon baselayer, the rear metallized hexagonal-prism ridges are coated to avertical height of roughly 2 to 20 microns depending on the hexagonalprism unit cell dimensions. For single-aperture cells fabricated usinghoneycomb prism TFSC substrates with a rear flat silicon base layer,only the hexagonal base interconnect ridges are coated. Forsingle-aperture cells fabricated using honeycomb prism TFSC substrateswith a rear flat silicon base layer and an integrated rear base mirror,the coating may cover the entire rear base mirror bottom surface ifdesired. Step 2358 involves automated TFSC placement and soldering (orcuring of epoxy). TFSCs are automatically picked and placed in aclosely-packed array on the frontside of the PCB. The rear side of eachcell sits on its designated site on the frontside of the double-sidedPCB with patterned copper interconnects. The TFSC rear hexagonal prismbase interconnect is soldered to the PCB frontside silver-coatedpatterned copper islands using thermal or ultrasonic soldering. In caseof using epoxy instead of solder, the epoxy layer is cured using thermaland/or IR/UV curing. The protective thin-film shunt diodes are mountedand soldered (or epoxied) on the PCB backside. An optional step is toflash coat the metal regions with a thin layer of highly reflectivesilver. Step 2360 involves final solar module assembly and lamination. Astack of low-reflection tempered (in one embodiment, also textured) topglass, an encapsulant layer, the cell-mounted PCB, another encapsulantlayer and a Tedlar or polyvinyl fluoride back sheet is prepared. Next,the module stack assembly is hermetically sealed and packaged, forinstance, using vacuum-pressure lamination.

FIG. 177 shows a cross-sectional view 2370 of another embodiment of asolar module structure. Instead of a top encapsulate layer (EVA) 2344,and an anti-reflection-coated (ARC) tempered glass 2346, as shown inFIG. 175, there is a single frontside protective layer andanti-reflective coating layer 2372. The frontside protective layer andanti-reflective coating (ARC) layer 2372 is formed by liquid spraycoating/curing, liquid roller coating/curing, liquid-dip coating/curing,plasma spray coating, or another suitable low-temperature coatingtechnique. This frontside protective coating and ARC layer 2372 iseffectively textured for the coating layer as deposited as a result ofthe 3-D structure of the TFSCs (thus, no separate texturing process isneeded). This is due to the fact that the coating layer may have dips(low points) over the TFSC hexagonal-prism cavities and peaks (highpoints) over the hexagonal-prism emitter ridges. The frontsideprotective layer and anti-reflective coating layer 2372 may have acombined thickness in the range of tens to hundreds of microns. In oneembodiment, the thickness may be approximately 30 to 300 microns. Inaddition to providing an anti-reflection coating (ARC) function, thestacked frontside protective/ARC layer provides excellent protectionagainst weather/elements and force impact (e.g., hail impact) in actualoutdoor field operation. Since the frontside coating is effectively andautomatically textured as a result of the 3-D structure of the TFSCs,the use of a separate ARC layer on the frontside coating is optional.The textured coating may provide effective light trapping in thefrontside coating for effective coupling of a very high fraction (e.g.,greater than 95%) of the incident solar light intensity to the TFSCs.The frontside protective layers may also provide an optical waveguidingfunction to eliminate or reduce any reflection losses associated withthe top emitter contact metallization.

FIG. 178 outlines an alternative embodiment of an assembly process flow2380 for fabrication of reduced cost and reduced weight (lightweight)solar modules (corresponding to the solar module structure of FIG. 177).This flow is compatible with a fully automated module assembly. Thisprocess flow shows the assembly process without the use of a thick glassplate (thus, further reducing the weight, cost, and energy payback timeof the solar modules of this disclosure) and without an EVA encapsulantlayer on the top of the cells. The module topside (the frontside ofassembled cells) is covered with a hard protective glass-type layer (ifdesired, also including a top ARC layer) with a combined thickness onthe order of tens to hundreds of microns. As deposited, this frontsideprotective layer is effectively textured as a result of the 3-Dstructure of the TFSCs. The top layer may be formed by a liquid coatingtechnique (e.g., spray coating, liquid-dip coating, or roller coating)following by a thermal or UV curing process. The thermal (or UV) curefor the liquid-spray-coated (or liquid-dip coated or roller coated)protective/AR layers may be performed as a single step together with thevacuum-pressure thermal lamination process. This embodiment results in alightweight module assembly with reduced materials consumption, reducedcost, and reduced energy payback time. Step 2382 (providing PCB)corresponds to step 2352 in FIG. 176; step 2384 (PCB patterning andsilver flash coat) corresponds to step 2354; step 2386 (cellpreparation) corresponds to step 2356; and step 2388 (automated TFSCplacement) corresponds to step 2358. Step 2390 involves solar modulelamination. A stack of the cell-mounted PCB, an encapsulant layer, and aback sheet is prepared. Next, a suitable hermetic sealing/packagingprocess such as vacuum-pressure lamination is performed. Step 2392involves deposition of the solar module frontside protective coating(which may be automatically textured as deposited and provides efficientlight trapping for effective coupling to the TFSCs) layer and anoptional ARC layer. The frontside of the solar panel is coated with athin layer of protective material (e.g., a glass-type transparentmaterial) and an optional top anti-reflection coating (ARC) layer usinga suitable coating method. This coating (roughly tens to hundreds ofmicrons) may be performed using liquid spray coating, liquid rollercoating, liquid-dip coating, plasma spray coating or another suitablemethod. Next, a thermal/UV curing process is performed.

The hexagonal-prism 3-D TFSCs of this disclosure (both thesingle-aperture and dual-aperture cells with and without the rear baselayers) are inherently bifacial. The hexagonal-prism 3-D TFSCs of thisdisclosure (particularly hexagonal-prism cells without rear base layers)are uniquely suited for aesthetically appealing solar glass modules withuniform controlled light transmissivity for building façadeapplications. The hexagonal-prism 3-D TFSCs of this disclosure (thedesigns without rear base layers and without rear mirrors) provide veryuniform partial sunlight transmissivity through the cells. The averagelevel of sunlight transmissivity may be set by adjusting the prism unitcell aspect ratio (higher prism aspect ratios reduce the averagesunlight transmissivity through the cells).

FIG. 179 shows the schematic cross-sectional view 2400 of a solar glassassembly using the hexagonal-prism TFSCs of this disclosure for buildingfaçade (architectural solar glass) applications. This is an embodimentof solar module assembly of this disclosure wherein the semi-transparentversions of the hexagonal-prism TFSCs of this disclosure (primarily thedual-aperture cells without rear base layers and without rear mirrors)are used for partially transparent solar glass modules for buildingfaçade applications. This example shows the semi-transparenthexagonal-prism cells 2402 (the version without the rear base layer andwithout the rear mirror such that it provides some level of sunlight ordiffuse daylight transparency through the cell from frontside oroutdoors through the cell backside, to allow a portion of the incidentsunlight/daylight through the cell) mounted within a dual-paneargon-filled (gas-filled) low-E glass assembly. The partiallytransparent TFSCs of this disclosure are closely packed and placed onthe lower glass plate 2404 (the glass plate facing the building indoors)which is coated with an optically transparent (or semi-transparent)patterned cell interconnect layer 2406 to connect the cells in the solarglass in electrical series. The patterned cell interconnect layer 2406may be made of a transparent conductive oxide (TCO) such as Indium TinOxide (ITO), a thin semi-transparent layer of silver, or a combinationthereof. The top glass plate 2408 shown here may face the façadeoutdoors while the lower glass plate 2404 (the one with the patternedtransparent/semi-transparent interconnect 2406 formed on its innersurface) may face the building indoors. There is a sealed argon-filledspace 2410 between the glass plates 2404 and 2408. Further, there is asealing/support window frame 2412 shown. This design allows for a veryuniform level of partial light transparency through the dual-pane solarglass module, thus, providing an aesthetically appealing solar glassdesign for architectural solar glass applications. The level of partialtransparency may be set by the hexagonal-prism cell geometricalparameters such as the unit cell hexagonal aperture size and the unitcell aspect ratio H/d. The level of partial light transparency may beincreased by reducing the unit cell aspect ratio H/d and/or byincreasing the unit cell aperture diagonal dimension d (see FIGS. 121and 167). Conversely, the level of partial light transparency may belowered by increasing the unit cell aspect ratio H/d and/or bydecreasing the unit cell aperture diagonal dimension d. Moreover, it ispossible to use a partially transparent rear mirror layer (in oneembodiment, a thin silver layer formed on the glass plate to form adiffuse partial rear mirror) as part of the patterned cell interconnectformed on the glass plate holding the attached cells. The partiallyreflecting/partially transparent rear mirror increases the effectivecell conversion efficiency, while reducing the partial lighttransmissivity through the solar glass assembly.

FIG. 180 shows another view 2420, which is an enlarged, alternative viewof a portion of the solar glass module assembly shown in FIG. 179 forbuilding façade applications. This FIGURE has a magnified view of aportion of the solar glass with the hexagonal-prism cells (thus, therelative dimensions of the hexagonal prism cell and the solar glass arenot shown to scale). FIG. 180 shows frontside TFSC hexagonal emitterinterconnects 2422 and self-aligned backside hexagonal base contact2424. The distance 2426 between the top glass plate 2408 and bottomglass plate 2404 may be between 1 and 12 millimeters. Thehexagonal-prism cell parameters may be designed to allow for a desiredlevel of light transmission through the cell (e.g., roughly 10% to 90%).The level of average light transmissivity can be controlled by theaspect ratio of the TFSCs.

FIG. 181 shows a view 2430 of a representative patternedsemi-transparent or transparent electrically conductive layer 2406 usedfor connecting the honey-comb-prism TFSCs placed within the solar glassassembly in series (such as a transparent conductive oxide—TCO includingindium-tin-oxide or ITO layer, or a thin semi-transparent layer ofsilver, or a combination thereof; which may also include a partiallytransparent cell rear mirror made of a suitable material such as anultrathin semitransparent layer of silver) formed on a glass plate 2434such as the lower glass plate 2404 of FIG. 179. This example showsconnection of 6×4=24 TFSCs in series within a solar glass moduleassembly. Of course, a similar patterning methodology may be used forconnecting any number of TFSCs in series, or in a combination ofseries/parallel configuration within the solar glass assembly. Seriesconnection of all the cells within a solar glass module assembly is apreferred electrical connection method (in order to step up the solarglass output voltage, while maintaining the solar glass module currentat the TFSC current level). This pattern also shows the outputelectrical leads 2436 of the solar module (solar glass) assembly. Thesolar glass power electrical leads 2436 may be fed through the solarglass frame assembly via a junction box for electrical connections tothe adjacent solar glass modules. Patterned IR mirror and cellinterconnects 2438 are visible to transparent light. The pattern ofdeposited thin film layer (or multiple layer structure) is formed bysputtering and/or plating. Note that the clear spaces shown betweenisland and lines are typically smaller than those shown (FIGURE not toscale).

FIG. 182 shows an alternative embodiment of a module assembly processflow 2440 for solar glass applications. This embodiment outlinesfabrication of semi-transparent solar glass modules for building façadeapplications (corresponding to the solar module structures of FIGS. 179,180, and 181). This solar glass module assembly flow is compatible witha fully automated solar glass module assembly. This flow shows theassembly process using a dual-pane low-E glass structure (other glassstructures may be employed as well). This embodiment results in alightweight solar glass module assembly with reduced materialsconsumption, reduced cost, and reduced module energy payback time. Instep 2442, solar glass manufacturing starts with a first glass platewhich may serve as the indoors side of a low-E architectural glassassembly for building façade. The glass area may be in a range from lessthan one m² to several m² depending on the application. Step 2444involves formation of (semi)-transparent cell interconnect pattern onfirst glass plate. The glass plate is cleaned, and a patterned layer ofoptically transparent or semi-transparent electrically conducting layeris deposited to serve as the cell electrical interconnect plane. Thepatterned interconnect layer may be made of a transparent conductiveoxide (TCO) such as Indium-Tin-Oxide (ITO), a thin semi-transparentlayer of silver, or a combination thereof. The patterned layer may beformed by physical-vapor deposition (PVD) through a shadow mask oranother suitable technique. Step 2446 involves cell preparation forautomated TFSC placement and attachment. The rear hexagonal metallizedside of the TFSCs is roller coated with lead-free solder or anelectrically conductive and thermally-conductive epoxy paste/liquid. Forcells fabricated using a honeycomb-prism TFSC substrate without a rearflat silicon base layer, the rear metallized hexagonal-prism ridges arecoated to a vertical height of roughly 1 to 20 microns depending on thehexagonal prism unit cell and base metal contact coverage dimensions.This process coats the base hexagonal array interconnects and theemitter wrap-around/wrap-through interconnects in preparation for cellplacement and attachment. Step 2448 involves automated TFSC placementand soldering (or curing of epoxy). TFSCs are automatically picked andplaced in a closely-packed array on the glass plate surface with thepatterned (semi)-transparent interconnects. The rear base sides ofhoneycomb-prism cells are placed on the glass plate. The TFSC rearhexagonal prism base interconnect is soldered (attached) to thepatterned cell interconnect layer on glass using thermal or ultrasonicsoldering. In case of using epoxy instead of solder, the epoxy is curedusing thermal or UV curing. Step 2450 involves automated solarglass/module assembly. In one embodiment, the solar glass moduleassembly is prepared in an atmospheric argon-filled automated assemblyambient by: mounting the glass plate with the attached cells onto asolar glass frame (e.g., a metallic frame such as aluminum frame with aperipheral seal); and attaching a glass plate (in one embodiment with anAR coating (ARC) layer) in parallel to and spaced apart (e.g., byroughly 1 to 30 millimeters) from the other glass plate (comprising thecells), to the solar glass frame such that the cells are confined withinan argon-filled cavity formed between the two glass plates sealed by themetallic frame. This forms the low-E solar glass assembly with the cellsconfined and protected within the argon-filled cavity. The solar glassmodule frame also provides the electrical lead feedthroughs which areattached to the leads from the patterned interconnect. Module frameperipheral seals maintain the argon-filled cavity and prevent gasleakage.

One important consideration in the TFSC and module interconnects is thetotal power loss associated with the electrical interconnects in theTFSCs and the solar module assembly. The hexagonal-prism 3-D c-Si TFSCand PCB-based module designs of this disclosure effectively address thisissue, resulting in very low interconnect ohmic losses in the cells andwithin the module. This feature (in conjunction with the highlyefficient packing of the TFSCs on the PCB-based solar module assembly)substantially narrows the efficiency gap between the TFSCs and the solarmodule assembly in the technology of this disclosure.

The next section relates to the basic calculations of the emittercontact metallization ohmic losses in the hexagonal-prism 3-D TFSCs ofthis disclosure. The calculations of ohmic losses for emitter contactmetallization are also applicable to the hexagonal base contactmetallization. However, since several embodiments of this disclosuremount the hexagonal prism 3-D TFSCs on patterned printed circuit boards(PCBs), the base contact metallization is electrically connected in aplanar format to a very high conductivity copper pad; this substantiallyreduces the base interconnect ohmic losses (compared to the emitterinterconnect ohmic losses). Therefore, in practical embodiments of thisdisclosure, the interconnect ohmic losses are dominated by the emittercontact metallization.

FIG. 183 may be used for reference with an approximate analyticalcalculation of the TFSC interconnect ohmic losses, assuming a circularsubstrate with hexagonal-prism array of unit cells base on the celldesign embodiments of this disclosure. Since the overall cellinterconnect ohmic losses are dominated by the top emitter contactmetallization, the ohmic power loss due to the hexagonal emitter contactmetallization is calculated as a function of cell current at maximumpower and emitter contact metal vertical height coverage ratio L/d(ratio of the height of emitter contact metal coverage on the prismsidewall to the prism unit cell long hexagonal diagonal dimension). Theanalytical calculations shown here were used to produce the plots shownin the following FIGURES (FIGS. 184-189). The calculations performed andtrends obtained for round substrates are also approximately applicableto square-shaped TFSC substrates.

For the following calculations: I₀ is the total cell current at peakpower; R_(thm) is the sheet resistance of top hexagonal-coverage emittercontact metal; C is the effective flat surface coverage of hexagonalemitter contact metal with vertical height L; R_(eff)=R_(thm)/C, whereR_(eff) is the effective flat surface sheet resistance of top contactmetal; A=(πa²)/4; and J₀=(4I₀)/(πa²).

Interconnect Ohmic Losses @ Max Cell Power:

P ₁≅(R _(eff) I ₀ ²)/(8π)

C=[(8√3)/3](L/d)

R _(eff)=(√3/8)(d/L)R _(thm)

P ₁≅(R _(thm) I ₀ ²)[√3/(64π)(d/L)≅8.62×10⁻³(R _(thm) I ₀ ²)(d/L)

FIGS. 184 through 189 show plots of the calculated hexagonal-prism 3-DTFSC interconnect (due to the dominant emitter contact metallization)ohmic losses versus L/d (ratio of the vertical coverage height of theemitter contact metal coverage on the prism sidewall to the longdiagonal dimension of the hexagonal aperture of the hexagonal-prism unitcell), for various values of emitter contact metal sheet resistance(R_(thm)). Assuming a cell efficiency of 20%, a 200 mm×200 mmsquare-shaped cell based on one of the embodiments of this disclosureproduces roughly 8 W of photogenerated power (AM1.5) and a cell currentof roughly 12 A. Thus, in order to limit the maximum emitter contactmetallization ohmic losses to roughly 1% of the peak photogeneratedpower of roughly 8 W, the ohmic power losses should be limited to 0.08W.

FIG. 184 shows the interconnect (emitter contact metallization) ohmiclosses at maximum cell power (200 W/m²) versus the ratio of emittercontact metal coverage height (coverage height of emitter contact metalon the prism unit cell sidewall) to hexagonal aperture diagonaldimension (L/d) for an emitter contact metal sheet resistance ofR_(thm)=0.002 Ω/square (assuming a silver bulk resistivity of roughly1.6 μΩ/square, this corresponds to an 8 microns thick silver layer usedas the emitter contact metallization layer). In this case, L/d of morethan 0.03 may meet the requirement of less than 1% interconnect ohmiclosses (power loss less than 0.08 W). Thus, for d=150 microns, L≧4.5microns may meet the negligible (<1%) interconnect power lossrequirement. Similarly for d=300 microns, L≧9 microns may meet the lessthan 1% interconnect loss requirement.

FIG. 185 shows interconnect (emitter contact metallization) ohmic lossesat maximum cell power (200 W/m²) versus the ratio of emitter contactmetal vertical coverage height (coverage height of emitter contact metalon the prism unit cell sidewall) to hexagonal aperture diagonaldimension (L/d) for an emitter contact metal sheet resistance ofR_(thm)=0.005 Ω/square (assuming a silver bulk resistivity of roughly1.6 μΩ/square, this corresponds to a 3.2 micron thick silver layer usedas the emitter contact metallization layer). In this case, L/d of morethan 0.07 may meet the requirement of less than 1% interconnect ohmiclosses (power loss less than 0.08 W). Thus, for d=150 microns, L≧10.5microns may meet the negligible (<1%) interconnect power lossrequirement. Similarly for d=300 microns, L≧21 microns may meet the lessthan 1% interconnect loss requirement.

FIG. 186 shows interconnect (emitter contact metallization) ohmic lossesat maximum cell power (200 W/m²) versus the ratio of emitter contactmetal coverage height (coverage height of emitter contact metal on theprism unit cell sidewall) to hexagonal aperture diagonal dimension (L/d)for an emitter contact metal sheet resistance of R_(thm)=0.0075 Ω/square(assuming a silver bulk resistivity of roughly 1.6 μΩ/square, thiscorresponds to a 2.1 micron thick silver layer used as the emittercontact metallization layer). In this case, L/d of more than 0.12 maymeet the requirement of less than 1% interconnect ohmic losses (powerloss less than 0.08 W). Thus, for d=150 microns, L≧18 microns may meetthe negligible (less than 1%) interconnect power loss requirement.Similarly for d=300 microns, L≧36 microns may meet the <1% interconnectloss requirement. If the interconnect ohmic loss limit is raised toroughly 2% of the photogenerated power (i.e., 0.02×8=0.16 W), L/d>0.06may meet the requirement of less than 2% interconnect ohmic losses(power loss less than 0.16 W). Thus, for d=150 microns, L≧9 microns maymeet this revised interconnect power loss requirement. Similarly ford=300 microns, L≧18 microns may meet the <2% interconnect lossrequirement.

FIG. 187 shows the emitter contact metal ohmic losses at maximum cellpower (200 W/m²) versus the ratio of emitter contact metal coverageheight (coverage height of emitter contact metal on the prism unit cellsidewall) to hexagonal aperture diagonal dimension (L/d) forR_(thm)=0.010 Ω/square (corresponding to a 1.6 micron thick silver layerused as the emitter contact metallization layer).

FIG. 188 shows the emitter contact metal ohmic losses at maximum cellpower (200 W/m²) versus the ratio of emitter contact metal coverageheight (coverage height of emitter contact metal on the prism unit cellsidewall) to hexagonal aperture diagonal dimension (L/d) forR_(thm)=0.015 Ω/square (corresponding to a 1.07 micron thick silverlayer used as the emitter contact metallization layer).

FIG. 189 shows the emitter contact metal ohmic losses at maximum cellpower (200 W/m²) versus the ratio of emitter contact metal coverageheight (coverage height of emitter contact metal on the prism unit cellsidewall) to hexagonal aperture diagonal dimension (L/d) forR_(thm)=0.020 Ω/square (corresponding to a 0.8 micron thick silver layerused as the emitter contact metallization layer).

As shown in FIGS. 184 through 189, as the emitter contact metal (e.g.,silver) sheet resistance is increased (or the emitter contact metalthickness is reduced), the vertical coverage of the emitter contactmetal over the prism sidewall should be increased (as a fraction of thehexagonal prism unit cell aperture diameter) in order to maintain theinterconnect ohmic losses below a pre-specified threshold value (e.g.,less than 1%). In practice, the desired emitter contact metallizationmay comprise silver with a thickness on the order of 3 to 12 micronsthick and with a vertical height coverage on the order of 5 to 20microns.

In summary, the disclosed subject matter provides methods formanufacturing three-dimensional single and dual aperture thin-film solarcells with and without rear mirrors. The three-dimensional thin-filmsolar cell comprises a semiconductor substrate with self-alignedselective emitter regions and self-aligned base diffusion regions. Thethree-dimensional thin-film solar cell further includes self-alignedemitter contact metallization regions and self-aligned base contactmetallization regions.

The foregoing description of the preferred embodiments is provided toenable any person skilled in the art to make or use the claimed subjectmatter. Various modifications to these embodiments will be readilyapparent to those skilled in the art, and the generic principles definedherein may be applied to other embodiments without the use of theinnovative faculty. Thus, the claimed subject matter is not intended tobe limited to the embodiments shown herein but is to be accorded thewidest scope consistent with the principles and novel features disclosedherein.

1. A method for manufacturing a three-dimensional thin-film solar cell,comprising: forming a three-dimensional thin-film solar cell substrateby the steps of: forming a sacrificial layer on a template, saidtemplate comprising a template substrate, said template substratecomprising a plurality of posts and a plurality of trenches between saidplurality of posts; subsequently depositing a semiconductor layer;selectively etching said sacrificial layer; and releasing saidsemiconductor layer from said template; doping select portions of saidthree-dimensional thin-film solar cell substrate with a first dopant;doping select portions of said three-dimensional thin-film solar cellsubstrate with a second dopant; and forming emitter metallizationregions and base metallization regions.
 2. The method for manufacturinga three-dimensional thin-film solar cell of claim 1, wherein said stepof doping select portions of said three-dimensional thin-film solar cellsubstrate with a first dopant comprises doping select portions of thetop of said three-dimensional thin-film solar cell substrate with afirst dopant.
 3. The method for manufacturing a three-dimensionalthin-film solar cell of claim 1, wherein said step of doping selectportions of said three-dimensional thin-film solar cell substrate with asecond dopant comprises doping select portions of the bottom of saidthree-dimensional thin-film solar cell substrate with a second dopant.4. The method for manufacturing a three-dimensional thin-film solar cellof claim 1, further comprising forming emitter junction regions and basediffusion regions.
 5. The method for manufacturing a three-dimensionalthin-film solar cell of claim 4, wherein said step of forming emitterjunction regions and base diffusion regions comprises forming selectiveemitter junction regions and selective base diffusion regions.
 6. Themethod for manufacturing a three-dimensional thin-film solar cell ofclaim 4, wherein said step of forming emitter junction regions and basediffusion regions comprises forming self-aligned emitter junctionregions and self-aligned base diffusion regions.
 7. The method formanufacturing a three-dimensional thin-film solar cell of claim 6,wherein said step of forming self-aligned emitter junction regions andself-aligned base diffusion regions comprises forming self-alignedemitter junction regions and self-aligned base diffusion regions usingself-aligned processing.
 8. The method for manufacturing athree-dimensional thin-film solar cell of claim 1, wherein said step offorming a three-dimensional thin-film solar cell substrate comprisesforming a three-dimensional thin-film solar cell substrate with aplurality of single-aperture unit cells.
 9. The method for manufacturinga three-dimensional thin-film solar cell of claim 1, wherein said stepof forming a three-dimensional thin-film solar cell substrate comprisesforming a three-dimensional thin-film solar cell substrate with aplurality of dual-aperture unit cells.
 10. The method for manufacturinga three-dimensional thin-film solar cell of claim 1, wherein saidsacrificial layer comprises a porous semiconductor layer.
 11. The methodfor manufacturing a three-dimensional thin-film solar cell of claim 1,wherein said sacrificial layer comprises a porous silicon layer.
 12. Themethod for manufacturing a three-dimensional thin-film solar cell ofclaim 1, wherein said sacrificial layer comprises a Ge_(x)Si_(1-x)layer.
 13. The method for manufacturing a three-dimensional thin-filmsolar cell of claim 1, wherein said semiconductor layer comprises asilicon layer.
 14. The method for manufacturing a three-dimensionalthin-film solar cell of claim 13, wherein said silicon layer comprises acrystalline silicon layer.
 15. The method for manufacturing athree-dimensional thin-film solar cell of claim 1, wherein said step ofdoping select portions of said three-dimensional thin-film solar cellsubstrate with a first dopant comprises selectively coating the top ofsaid three-dimensional thin-film solar cell substrate with a firstdopant, curing said first dopant to form a first cured dopant, andperforming a thermal anneal process.
 16. The method for manufacturing athree-dimensional thin-film solar cell of claim 15, further comprisingselectively removing said first cured dopant.
 17. The method formanufacturing a three-dimensional thin-film solar cell of claim 1,wherein said step of doping select portions of said three-dimensionalthin-film solar cell substrate with a second dopant comprisesselectively coating the bottom of said three-dimensional thin-film solarcell substrate with a second dopant, curing said second dopant to form asecond cured dopant, and performing a thermal anneal process.
 18. Themethod for manufacturing a three-dimensional thin-film solar cell ofclaim 17, further comprising selectively removing said second cureddopant.
 19. The method for manufacturing a three-dimensional thin-filmsolar cell of claim 1, wherein said first dopant comprises an n-typedopant and said second dopant comprises a p-type dopant.
 20. The methodfor manufacturing a three-dimensional thin-film solar cell of claim 19,wherein said n-type dopant comprises phosphorus and said p-type dopantcomprises boron.
 21. The method for manufacturing a three-dimensionalthin-film solar cell of claim 1, wherein said first dopant comprises ap-type dopant and said second dopant comprises an n-type dopant.
 22. Themethod for manufacturing a three-dimensional thin-film solar cell ofclaim 21, wherein said n-type dopant comprises phosphorus and saidp-type dopant comprises boron.
 23. The method for manufacturing athree-dimensional thin-film solar cell of claim 1, wherein said step offorming emitter metallization regions and base metallization regionscomprises forming self-aligned emitter metallization regions andself-aligned base metallization regions.
 24. The method formanufacturing a three-dimensional thin-film solar cell of claim 23,wherein said step of forming self-aligned emitter metallization regionsand self-aligned base metallization regions comprises formingself-aligned emitter metallization regions and self-aligned basemetallization regions using self-aligned processing.
 25. The method formanufacturing a three-dimensional thin-film solar cell of claim 1,wherein said step of forming emitter metallization regions and basemetallization regions comprises forming emitter metallization regionsand base metallization regions using fire-through processing.
 26. Themethod for manufacturing a three-dimensional thin-film solar cell ofclaim 1, wherein said step of forming emitter metallization regions andbase metallization regions comprises forming emitter metallizationregions and base metallization regions using plating.
 27. The method formanufacturing a three-dimensional thin-film solar cell of claim 1,further comprising mounting the three-dimensional thin-film solar cellon a rear mirror.
 28. A method for manufacturing a three-dimensionalthin-film solar cell, comprising: forming a three-dimensional thin-filmsolar cell substrate by the steps of: forming a sacrificial layer on atemplate; subsequently depositing a semiconductor layer; and releasingsaid semiconductor layer from said template; doping select portions ofsaid three-dimensional thin-film solar cell substrate with dopants; andforming metallization regions.